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Data Sheet, V2.3, Nov. 2003
TC11IB
32-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
Edition 2003-11 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2003. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, V2.3, Nov. 2003
TC11IB
32-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
TC11IB Advance Information Revision History: Previous Version:
2003-11 V1.1, 2002-03 V1.2, 2002-04 V1.3, 2002-09 V2.0, 2002-12 V2.1, 2003-02 V2.2, 2003-07
V2.3
Page 71
Subjects (major changes since last revision) Power supply current is updated.
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
32-Bit Single-Chip Microcontroller TriCore Family Advance Information
TC11IB
* High Performance 32-bit TriCore CPU with 4-Stage Pipeline running at 96MHz Clock * Dual Issue super-scalar implementation - MAC Instruction maximum triple issue * Circular Buffer and bit-reverse addressing modes for DSP algorithms * Flexible multi-master interrupt system * Very fast interrupt response time * Hardware controlled context switch for task switch and interrupts * Windows CE compliant Memory Management Unit (MMU) * 64 kByte of on-chip SRAM for data and time critical code * Independent Peripheral Control Processor (PCP) for low level driver support with 20 kByte code / parameter memory * eDRAM Local Memory Unit (LMU) with 512 KBytes Code/data Memory. * ComDRAM with 1MBytes DRAM Memory * High Performance Local Memory Bus (LMB) for fast access between Caches and onlocal memories and Fast-FPI Interface. * Two On-chip Flexible Peripheral Interface Buses (Fast FPI Bus and Slow FPI Bus) for interconnections of functional units * Flexible External Bus Interface Unit (EBU) used for communication with external data memories such as PC 100 SDRAM, Burst Flash and SRAM etc. and external peripheral units, including Intel style and Motorola style peripherals. * On-Chip Peripheral Units - Two Multifunctional General Purpose Timer Units (GPTU0 & GPTU1) with three 32bit timer/counters each - Asynchronous/Synchronous Serial Channels (ASC) with IrDA data transmission, receive/transmit FIFOs, parity, framing and overrun error detection - High Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - Asynchronous Serial Interface (16X50) with programmable XON/XOFF characters, Baudrate generator, receive/transmit FIFOs and standard modem interface support. - 16 MHz MultiMediaCard Interface (MMCI), a glueless interface to MultiMediaCard Bus, with bus clock generation, CRC protection and up to 2 MByte/s data communication. - Fast Ethernet Controller with 10/100 Mbps MII-Based physical devices support. - PCI V2.2 Interface with PCI Bus Power Management and DMA data transfer. - Watchdog Timer and System Timer * Six 16-bit digital I/O ports * On-Chip Debug Support (OCDS)
Data Sheet 1 V2.3, 2003-11
TC11IB
* * * *
Power Management System Clock Generation Unit with PLL Ambient temperature under bias: -25 C to +85 C P-BGA-388-2 package
Data Sheet
2
V2.3, 2003-11
Figure 1
LM (Local M ory Bus) 96 M B em Hz, 64 Bit MU M TC11IB Block Diagram 1.8-3.3 V 128 64 LM U 512 KB eDRAM TriCore 1.3 CPU
OCDS
FPI Interface
Data Sheet
VDD VSS
16 O CDS2 O CDSE 8 Control BRKIN BRKO UT PLL 96 & 48 M Hz 5 Cerberus JTAG XTAL1 XTAL2 DM U (Data M ory Unit) em 24 KB Scratch Pad RAM 8 KB Data Cache Interrupt Trace & O CDS PM U (Program M ory Unit) em 24 KB Scratch Pad RAM 8 KB Instruction Cache 4 K Data SRAM SCU (PW R) Power M anagem ent, W atchdog Tim er, Reset FFI Bridge Interrupt 16 K Code SRAM Boot-RO M 16 Kbytes Slow FPI Bus (Flexible Peripheral Interface) 48 M Hz, 32 Bit BCU1 Slow FPI BUS PCP JTAG I/O Fast Ethernet M CI M 16x50 XO N/ XO FF ASC FIFO , IrDA SSC G PTU1 3 Tim ers G PTU0 3 Tim ers 15 PO RT2 M DIO RxCLK TxCLK
MCB04939
Block Diagram
32
AD[31:0]
A[23:0]
24
EBU_LM B
LFI Bridge
TC11IB Block Diagram
1 3 8 2 PO RT1 16 3 8 8 PO RT0 16 16
EBU_Control
33
3
BCU0 Fast FPI BUS
Com DRAM 1 M 96 M B, Hz
Fast FPI Bus 96 M Hz, 32 Bit
32
P_AD[31:0]
P_Control
20
PCI V2.2 33 M Hz (DM Support) + A Power M anagem ent
3
9
PO RT5
PO RT4
PO RT3
16
16
16
V2.3, 2003-11
TC11IB
External External Interrupts Interrupts
TC11IB
Logic Symbol
A lternate F unctions PORST HDRST NMI C F G [0:3] C P U C LK RD R D /W R W A IT SVM H LD A BREQ A LE RAS CAS C S [0:6] CSEMU C S G LB CSOVL CSFPI CKE M R _W RMW H O LD E B U C LK BAA ADV A C LK C M D E LA Y M II_T xC LK M II_R xC LK M II_M D IO TESTM ODE T M _C T R L1 T M _C T R L2 C LK 42 P LL96_C trl P LL42_C trl X T A L1 X T A L2 V DDOSC V SSOSC V DDPLL96 V SSPLL96 V DDPLL42 V SSPLL42 P ort 0 16-B it 4 P ort 1 16-B it P ort 2 16-B it P ort 3 16-B it P ort 4 16-B it P ort 5 16-B it A D [0:31] B C [0:3] A [0:23] OCDS/ JT A G C ontrol O C D S 2P S [0:4] O C D S 2P C [0:7] O C D S 2B R K [0:2] P _A D [0:31] TC 11IB P _C /B E [0:3] P _P A R P _S E R R P _P E R R P _S T O P P _D E V S E L P _T R D Y P _F R A M E P _IR D Y P _LO C K P _IN T A P _IN T B P _P M E P _R E Q P _G N T P _ID S E L P _C LK 33 V LM UR EF V C O M REF V DDDRAM V DDP V DD V SS E B U C ontrol G P T U 0/1 S S C 0/1, M M C I, A S C , 16x50 E thernet, M M C I E xternal Interrupts MMCI
G eneral C ontrol
7
E B U C ontrol
O C D S / JT A G C ontrol
E thernet C lock
PCI
TEST
O scillator / P LL
2 20 21 52
D igital C ircuitry P ow er S upply
M C B 04945
Figure 2
TC11IB Logic Symbol
Data Sheet
4
V2.3, 2003-11
TC11IB
Pin Configuration
1 A HD RST
OCDS 2P S [2] OCDS 2P C [7]
2 P 1.15
3 P 1.13 P 1.14 PO RST
4 P 1.11
5 P 1.7 P 1.8
6 P 1.4 P 1.5
7 P 1.0 P 1.1
8 P 2.12 P 2.14
9 P 2.10 P 2.11
10
11
12
13
14
15
16
17
18 P 2.3
19 P 2.1
20 A LE
21 CS G LB
22 BAA
23 H LD A
24
25
26 R eser A ved
V DD V SS M II_ M II_ X T A L2 X T A L1 M D IO T xC LK P LL42 P LL96
P 2.8
V LM U
REF P 2.7
V DD
DRAM P 2.5
A [20] A D [3 1]
B
NM I CPU C LK
V DD
P 1.12
V DD
P LL42 V D D C T R L P LL96
V DD
OSC
P LL96 CTRL
P 2.2
ADV
CSFPI CS OVL SVM
CM DE BREQ LA Y
M R _W H O LD
A [21] A D [23] A D [3 0] A D [29] B
C
P 1.9
P 1.6
P 1.2
P 2.15
P 2.13
P 2.9
V SS V TM TM M II_ R x C LK C T R L2 P LL42 S S O S C C T R L1 V DDP
C LK 42
P 2.6
P 2.4
P 2.0
W A IT
A [22] A D [22] A D [2 1] A D [28] C
D
OCDS OCDS OCDS 2P C [4] 2P S [1] 2P S [4]
V SS
P 1.10
V DD
P 1.3
V DDP
V SS
V DD
V SS
V DDP
R eser ved
V DDP
V DD
V SS
V DDP
V DD
A [23]
V SS
A D [20] A D [2 7] A D [26] D
E
OCDS OCDS OCDS OCDS 2P C [3] 2P C [6] 2P S [0] 2P S [3]
A D [19] A D [18] A D [2 5] A D [24] E
F OCDS OCDS OCDS 2P C [1] 2P C [2] 2P C [5] G
V DD
V DD
A D [17] A D [1 6] A D [15] F
OCDS OCDS OCDS OCDS 2 B R K 2B R K 2B R K 2P C [0] [0] [1] [2]
H
V DD
CFG [2] P 0.0
OCDS _E
BR K _IN BR K _OUT
388 -P in P -B G A P ackag e P in C o nfig uration (top view ) for T C 1 1IB
A D [7]
A D [6] A D [1 4] A D [13] G
V DDP V SS V DD V DDP
P 0.7
V DDP V SS V DD V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V DDP
A C LK
A D [5] A D [1 2] A D [11] H
J
CFG [3] CFG [0] P 0.2
A D [4] A D [10] A D [9]
J
K
CFG [1] P 0.1
A D [2]
A D [3]
A D [8]
K
L
P 0.3
A D [1]
A D [0]
B C [2]
L
M
P 0.4
P 0.5
P 0.6
B C [3] RD/ WR C S [6]
B C [0]
B C [1] EBU C LK CKE
M
N
P 0.8
P 0.9
P 0.10
V DDP V SS
P 3.1
V SS V DDP
A [17]
CAS
N
P
P 0.11
P 0.12
P 0.13
RAS
P
R
P 0.14
P 0.15
P 3.0
A [18]
A [19]
C S [5]
R
T
P 3.2
V DD
P 3.5
P 3.3
V DDP V DD V SS V DDP
P 3.15
V DDP V DD V SS V DDP
C S [4]
A [16]
A [15]
A [14]
T
U
P 3.4
P 3.6
A [12]
A [11]
A [13]
U
V
P 3.7
P 3.8
P 3.9
A [1]
A [9]
A [10]
V
W
V DD
P 3.12 P 4.0
P 3.10
P 3.11
A [2]
A [7]
A [8]
W
Y
P 3.13 P 4.1
P 3.14 P 4.2
A [3]
A [4]
A [6]
Y
AA
V DD
P 4.6
V DD
RMW P 5.3
C S [3]
A [5]
A [0]
AA
AB
P 4.3
P 4.4
P 4.5
C S [0]
C S [2]
RD C S [1] P _A D [0]
AB
AC
P 4.7
P 4.8
P 4.9
V SS
P 5.2
V DD
P 5.9
P 5.10
V DDP
TM S
V SS
TDI
V DD
VC OM REF P_ IN T A P_ IN T B
V DDP
P_ GNT P_ R EQ
P_ PM E
V DDP
V SS
P _A D [26] P _A D [24]
P_ ID S E L
V DDP
V DD
V SS
V DDP
P_ STOP
V DD
P _A D [15] P _A D [14]
P _A D [13]
V SS
P _A D [9] P _A D [7] P _A D [8] 23
P _C /B E C S [0] EM U
AC
AD
P 4.10
P 4.11
P 4.14
P 5.6
P 5.13
P _A D P _A D [30] [28] P _A D P _A D [29] [27]
P _A D [22] P _A D [23]
P_ P _A D P _A D P_ [20] [18] FR A M E T R D Y
P_ PAR
P_ SER R
P _A D [11] P _A D [10]
P _A D [6] P _A D [4] P _A D [5] 24
P _A D [2] P _A D [1] P _A D [3] 25
AD
AE
P 4.12
P 4.13
P 5.1
P 5.5
P 5.8
P 5.12
P 5.15
TEST TRST M ODE
P _A D P _A D [19] [16]
P_ IR D Y
P_ LO C K
R eser AE ved R eser A F ved 26
AF
P 5.0 1
P 4.15 2
P 5.4 3
P 5.7 4
P 5.11 5
P 5.14 6
TCK 7
TDO 8
R e ser v ed
V DD P _C L K P _A D [31] D R A M 33
11 12 13
P _ P _C /B E P _A D P _A D P _C /B E P _A D P _A D P _C /B E P _D E V [3] [2] [1] [25] [21] [17] [12] SEL PER R
9
10
14
15
16
17
18
19
20
21
22
M C P 0495 0
Figure 3
TC11IB Pinning: P-BGA-388 Package (top view)
Data Sheet
5
V2.3, 2003-11
TC11IB
Table 1 Symbol P0
Pin Definitions and Functions Pin In PU/ Out PD1) I/O Functions Port 0 Port 0 serves as 16-bit general purpose I/O port, which is also used as input/output for the General Purpose Timer Units (GPTU0 & GPTU1) GPTU0_IO0 GPTU0 I/O line 0 GPTU0_IO1 GPTU0 I/O line 1 GPTU0_IO2 GPTU0 I/O line 2 GPTU0_IO3 GPTU0 I/O line 3 GPTU0_IO4 GPTU0 I/O line 4 GPTU0_IO5 GPTU0 I/O line 5 GPTU0_IO6 GPTU0 I/O line 6 GPTU0_IO7 GPTU0 I/O line 7 GPTU1_IO0 GPTU1 I/O line 0 GPTU1_IO1 GPTU1 I/O line 1 GPTU1_IO2 GPTU1 I/O line 2 GPTU1_IO3 GPTU1 I/O line 3 GPTU1_IO4 GPTU1 I/O line 4 GPTU1_IO5 GPTU1 I/O line 5 GPTU1_IO6 GPTU1 I/O line 6 GPTU1_IO7 GPTU1 I/O line 7
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15
K1 L3 L2 L1 M1 M2 M3 M4 N1 N2 N3 P1 P2 P3 R1 R2
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PUB PUB PUB PUB PUC PDC PDC PUC PUC PUC PUC PUC
Data Sheet
6
V2.3, 2003-11
TC11IB
Table 1 Symbol P1
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) I/O Functions Port 1 Port 1 serves as 16-bit general purpose I/O port, which also is used as input/output for the serial interfaces (SSC,ASC,16X50) and MultiMediaCard Interface (MMCI) SCLK SSC clock input/output line MRST SSC master receive / slave transmit input/output MTSR SSC master transmit / slave receive input/output MMCI_CLK MMCI clock output line MMCI_CMD MMCI command input/output line MMCI_DAT MMCI data input/output line ASC_RXD ASC receiver input/output line ASC_TXD ASC transmitter output line 16X50_RXD 16X50 receiver input line 16X50_TXD 16X50 transmitter output line 16X50_RTS 16X50 request to send output line 16X50_DCD 16X50 data carrier detection input line 16X50_DSR 16X50 data set ready input line 16X50_DTR 16X50 data terminal ready output line 16X50_CTS 16X50 clear to send input line 16X50_RI 16X50 ring indicator input line
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15
A7 B7 C7 D7 A6 B6 C6 A5 B5 C5 D5 A4 C4 A3 B3 A2
I/O I/O I/O O I/O I/O I/O O I O O I I O I I
PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC
Data Sheet
7
V2.3, 2003-11
TC11IB
Table 1 Symbol P2
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) I/O Functions Port 2 Port 2 serves as 16-bit general purpose I/O port, which is also used as input/output for Ethernet controller and MultiMediaCard (MMCI). MII_TXD0 Ethernet controller transmit data output line 0 MII_TXD1 Ethernet controller transmit data output line 1 MII_TXD2 Ethernet controller transmit data output line 2 MII_TXD3 Ethernet controller transmit data output line 3 MII_TXER Ethernet controller transmit error output line MII_TXEN Ethernet controller transmit enable output line MII_MDC Ethernet controller management data clock output line MMCI_VDDEN MMCI power supply enable output line MII_RXDV Ethernet Controller receive data valid input line MII_CRS Ethernet Controller carrier input line MII_COL Ethernet Controller collision input line MII_RXD0 Ethernet Controller receive data input line 0 MII_RXD1 Ethernet Controller receive data input line 1 MII_RXD2 Ethernet Controller receive data input line 2 MII_RXD3 Ethernet Controller receive data input line 3 MII_RXER Ethernet Controller receive error input line
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15
C18 A19 B18 A18 C17 B17 C16 B16 B10 C10 A9 B9 A8 C9 B8 C8
O O O O O O O O I I I I I I I I
PUC PDC PDC PUC PDC PDC PDC PDC PDC
Data Sheet
8
V2.3, 2003-11
TC11IB
Table 1 Symbol P3
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) I/O Functions Port 3 Port 3 serves as 16-bit general purpose I/O port, which is also used as input for external interrupts. INT0 External interrupt input line 0 INT1 External interrupt input line 1 INT2 External interrupt input line 2 INT3 External interrupt input line 3 INT4 External interrupt input line 4 INT5 External interrupt input line 5 INT6 External interrupt input line 6 INT7 External interrupt input line 7 INT8 External interrupt input line 8 INT9 External interrupt input line 9 INT10 External interrupt input line 10 INT11 External interrupt input line 11 INT12 External interrupt input line 12 INT13 External interrupt input line 13 INT14 External interrupt input line 14 INT15 External interrupt input line 15
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15
R3 R4 T1 T3 U1 U2 U3 V1 V2 V3 W2 W3 Y1 Y2 Y3 Y4
I I I I I I I I I I I I I I I I
Data Sheet
9
V2.3, 2003-11
TC11IB
Table 1 Symbol P4
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) I/O Functions Port 4 Port 4 is used as general purpose I/O port, 8 pins of which (P4.0 ~ P4.7) also serve as inputs for external interrupts. INT16 External interrupt input line 16 INT17 External interrupt input line 17 INT18 External interrupt input line 18 INT19 External interrupt input line 19 INT20 External interrupt input line 20 INT21 External interrupt input line 21 INT22 External interrupt input line 22 INT23 External interrupt input line 23
P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P4.8 P4.9 P4.10 P4.11 P4.12 P4.13 P4.14 P4.15
AA1 AA2 AA3 AB1 AB2 AB3 AB4 AC1 AC2 AC3 AD1 AD2 AE1 AE2 AD3 AF2
I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O
PDC PDC PDC PDC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC
Data Sheet
10
V2.3, 2003-11
TC11IB
Table 1 Symbol P5
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) I/O Functions Port 5 Port 5 serves as 16-bit general purpose I/O port, 3 pins of which (P5.0, P5.2 and P5.15) serve as output lines for MultiMediaCard Interface (MMCI) also. MMCI_DATRWMMCI data direction indicator output line MMCI_CMDRWMMCI command direction indicator output line
P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 HDRST
AF1 AE3 AD4 AC5 AF3 AE4 AD5 AF4 AE5 AD6 AC7 AF5 AE6 AD7 AF6 AE7 A1
O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O
PUC PUC PUC PUC PUC PDC PUC PUC PDC PUC PUC
MMCI_ROD
MMCI command line mode indicator output line
Hardware Reset Input/Reset Indication Output Assertion of this bidirectional open-drain pin causes a synchronous reset of the chip through external circuitry. This pin must be driven for a minimum duration. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog, power-down wake-up reset and eDRAM reset for a specific period of time. For a software reset, activation of this pin is programmable. Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. PORST is a fully asynchronous level sensitive signal.
PORST
C3
I
PUC
Data Sheet
11
V2.3, 2003-11
TC11IB
Table 1 Symbol NMI
Pin Definitions and Functions(cont'd) Pin B2 In PU/ Out PD1) I PUB Functions Non-Maskable Interrupt Input A high-to-low transition on this pin causes a NMI-Trap request to the CPU. Operation Configuration Inputs The configuration inputs define the boot options of the TC11IB after a hardware-invoked reset operation. Clock Output JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. JTAG Module Clock Input JTAG Module Serial Data Input JTAG Module Serial Data Output JTAG Module State Machine Control Input OCDS Enable Input A low level on this pin during power-on reset (PORST = 0) enables the on-chip debug support (OCDS). In addition, the level of this pin during poweron reset determines the boot configuration. OCDS Break Input A low level on this pin causes a break in the chip's execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. OCDS Break Output A low level on this pin indicates that a programmable OCDS event has occurred.
CFG0 CFG1 CFG2 CFG3 CPU CLK TRST
K2 K3 J1 J2 C2 AE8
I I I I O I
PDC PDC PUC PUC PUC PDC
TCK TDI TDO TMS OCDSE
AF7 AD9 AF8 AD8 H2
I I O I I
PUC PUC PUC PUC
BRKIN
H3
I
PUC
BRKOUT J3
O
Data Sheet
12
V2.3, 2003-11
TC11IB
Table 1 Symbol OCDS2 PS0 OCDS2 PS1 OCDS2 PS2 OCDS2 PS3 OCDS2 PS4 OCDS2 PC0 OCDS2 PC1 OCDS2 PC2 OCDS2 PC3 OCDS2 PC4 OCDS2 PC5 OCDS2 PC6 OCDS2 PC7 OCDS2 BRK0 OCDS2 BRK1 OCDS2 BRK2
Pin Definitions and Functions(cont'd) Pin E3 D2 B1 E4 D3 G1 F1 F2 E1 D1 F3 E2 C1 G2 G3 G4 In PU/ Out PD1) O O O O O O O O O O O O O O O O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Break Qualification Lines outputs Indirect PC Address Outputs Functions Pipeline Status Signal Outputs
Data Sheet
13
V2.3, 2003-11
TC11IB
Table 1 Symbol
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) Functions PCI Interface Address /Data Bus Input / Output Lines PCI Interface Address / Data Bus Line 0 PCI Interface Address / Data Bus Line 1 PCI Interface Address / Data Bus Line 2 PCI Interface Address / Data Bus Line 3 PCI Interface Address / Data Bus Line 4 PCI Interface Address / Data Bus Line 5 PCI Interface Address / Data Bus Line 6 PCI Interface Address / Data Bus Line 7 PCI Interface Address / Data Bus Line 8 PCI Interface Address / Data Bus Line 9 PCI Interface Address / Data Bus Line 10 PCI Interface Address / Data Bus Line 11 PCI Interface Address / Data Bus Line 12 PCI Interface Address / Data Bus Line 13 PCI Interface Address / Data Bus Line 14 PCI Interface Address / Data Bus Line 15 PCI Interface Address / Data Bus Line 16 PCI Interface Address / Data Bus Line 17 PCI Interface Address / Data Bus Line 18 PCI Interface Address / Data Bus Line 19 PCI Interface Address / Data Bus Line 20 PCI Interface Address / Data Bus Line 21 PCI Interface Address / Data Bus Line 22 PCI Interface Address / Data Bus Line 23 PCI Interface Address / Data Bus Line 24 PCI Interface Address / Data Bus Line 25 PCI Interface Address / Data Bus Line 26 PCI Interface Address / Data Bus Line 27 PCI Interface Address / Data Bus Line 28 PCI Interface Address / Data Bus Line 29 PCI Interface Address / Data Bus Line 30 PCI Interface Address / Data Bus Line 31 PCI Interface Parity Input / Output PCI Interface System Error Input / Output PCI Interface Parity Error Input / Output
P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_PAR P_SERR P_PERR
AD26 AE25 AD25 AF25 AE24 AF24 AD24 AE23 AF23 AD23 AE22 AD22 AF22 AC22 AE21 AD21 AE17 AF17 AD17 AE16 AD16 AF16 AD15 AE15 AE14 AF14 AD14 AE13 AD13 AE12 AD12 AF12 AE20 AF20
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

AD20 I/O
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol P_STOP P_C/BE0 P_C/BE1 P_C/BE2 P_C/BE3 P_IDSEL P_REQ P_GNT P_DEVS EL P_TRDY P_FRAM E P_IRDY P_LOCK P_INTA P_INTB P_PME MII_ TXCLK
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) PDC I/O I/O I/O I/O I O I/O Functions PCI Interface Stop Input / Output PCI Interface Command / Byte Enable Inputs / Outputs
AC20 I/O AC24 AF21 AF18 AF15
AC15 I AE11 AF19
PCI Interface ID Select Input PCI Interface Clock Input PCI Interface Bus Request Output PCI Interface Bus Grant Input PCI Interface Device Select Input / Output PCI Interface Target Ready Input / Output PCI Interface Frame Input / Output PCI Interface Initiator Ready Input / Output PCI Interface Lock Input PCI Interface Interrupt A Output PCI Interface Interrupt B Output PCI Interface Power Management Event Output Ethernet Controller Transmit Clock MII_TXD[3:0] and MII_TXEN are driven off the rising edge of the MII_TXCLK by the core and sampled by the PHY on the rising edge of the MII_TXCLK. Ethernet Controller Receive Clock MII_RXCLK is a continuous clock. Its frequency is 25 MHz for 100 Mbps operation, and 2.5 MHz for 10Mbps. MII_RXD[3:0], MII_RXDV and MII_EXER are driven by the PHY off the falling edge of MII_RXCLK and sampled on the rising edge of MII_RXCLK.
P_CLK33 AF11
AD11 I
AD19 I/O AD18 I/O AE18 AE19 AE10 AF10 A11 I/O I O O I
AC12 O
MII_ RXCLK
C11
I
PDC
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol MII_ MDIO
Pin Definitions and Functions(cont'd) Pin A10 In PU/ Out PD1) I/O PDA Functions Ethernet Controller Management Data Input / Output When a read command is being executed, data which is clocked out of the PHY will be presented on the input line. When the Core is clocking control or data onto the MII_MDIO line, the signal will carry the information. EBU_LMB Chip Select Output Line 0 EBU_LMB Chip Select Output Line 1 EBU_LMB Chip Select Output Line 2 EBU_LMB Chip Select Output Line 3 EBU_LMB Chip Select Output Line 4 EBU_LMB Chip Select Output Line 5 EBU_LMB Chip Select Output Line 6 Each corresponds to a programmable region. Only one can be active at one time. EBU_LMB Chip Select Output for Emulator Region EBU_LMB Chip Select Global Output EBU_LMB Chip Select Output for Overlay Memory EBU_LMB Chip Select Input for Internal FPI Bus For external master to select EBU_LMB as target in the slave mode EBU_LMB External Bus Clock Output Derived from LMBCLK as equal, half or one-fourth of the frequency.
CS0 CS1 CS2 CS3 CS4 CS5 CS6
AB24 AC26 AB25 AA24 Y23 R26 P24
O O O O O O O
PUC PUC PUC PUC PUC PUC PUC
CSEMU CSGLB CSOVL CSFPI
AC25 O A21 C20 B20 O O I
PUC PUC PUC PUC
EBUCLK
N26
O
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Functions EBU_LMB Address / Data Bus Input / Output Lines EBU_LMB Address / Data Bus Line 0 EBU_LMB Address / Data Bus Line 1 EBU_LMB Address / Data Bus Line 2 EBU_LMB Address / Data Bus Line 3 EBU_LMB Address / Data Bus Line 4 EBU_LMB Address / Data Bus Line 5 EBU_LMB Address / Data Bus Line 6 EBU_LMB Address / Data Bus Line 7 EBU_LMB Address / Data Bus Line 8 EBU_LMB Address / Data Bus Line 9 EBU_LMB Address / Data Bus Line 10 EBU_LMB Address / Data Bus Line 11 EBU_LMB Address / Data Bus Line 12 EBU_LMB Address / Data Bus Line 13 EBU_LMB Address / Data Bus Line 14 EBU_LMB Address / Data Bus Line 15 EBU_LMB Address / Data Bus Line 16 EBU_LMB Address / Data Bus Line 17 EBU_LMB Address / Data Bus Line 18 EBU_LMB Address / Data Bus Line 19 EBU_LMB Address / Data Bus Line 20 EBU_LMB Address / Data Bus Line 21 EBU_LMB Address / Data Bus Line 22 EBU_LMB Address / Data Bus Line 23 EBU_LMB Address / Data Bus Line 24 EBU_LMB Address / Data Bus Line 25 EBU_LMB Address / Data Bus Line 26 EBU_LMB Address / Data Bus Line 27 EBU_LMB Address / Data Bus Line 28 EBU_LMB Address / Data Bus Line 29 EBU_LMB Address / Data Bus Line 30 EBU_LMB Address / Data Bus Line 31 EBU_LMB Byte Control Line 0 EBU_LMB Byte Control Line 1 EBU_LMB Byte Control Line 2 EBU_LMB Byte Control Line 3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 BC0 BC1 BC2 BC3
L25 L24 K24 K25 J24 H24 G24 G23 K26 J26 J25 H26 H25 G26 G25 F26 F25 F24 E24 E23 D24 C25 C24 B24 E26 E25 D26 D25 C26 B26 B25 A25 M25 M26 L26 M24
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Functions EBU_LMB Address Bus Input / Output Lines EBU_LMB Address Bus Line 0 EBU_LMB Address Bus Line 1 EBU_LMB Address Bus Line 2 EBU_LMB Address Bus Line 3 EBU_LMB Address Bus Line 4 EBU_LMB Address Bus Line 5 EBU_LMB Address Bus Line 6 EBU_LMB Address Bus Line 7 EBU_LMB Address Bus Line 8 EBU_LMB Address Bus Line 9 EBU_LMB Address Bus Line 10 EBU_LMB Address Bus Line 11 EBU_LMB Address Bus Line 12 EBU_LMB Address Bus Line 13 EBU_LMB Address Bus Line 14 EBU_LMB Address Bus Line 15 EBU_LMB Address Bus Line 16 EBU_LMB Address Bus Line 17 EBU_LMB Address Bus Line 18 EBU_LMB Address Bus Line 19 EBU_LMB Address Bus Line 20 EBU_LMB Address Bus Line 21 EBU_LMB Address Bus Line 22 EBU_LMB Address Bus Line 23 EBU_LMB Read Control Line Output in the master mode Input in the slave mode. EBU_LMB Write Control Line Output in the master mode Input in the slave mode. EBU_LMB Wait Control Line EBU_LMB Supervisor Mode Output EBU_LMB Address Latch Enable Output EBU_LMB SDRAM Row Address Strobe Output EBU_LMB SDRAM Column Address Strobe Output
18 V2.3, 2003-11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 RD
AA26 V24 W24 Y24 Y25 AA25 Y26 W25 W26 V25 V26 U25 U24 U26 T26 T25 T24 R23 R24 R25 A24 B23 C23 D22 AB26
RD/WR
N24
I/O
PUC
WAIT SVM ALE RAS CAS
Data Sheet
C19 D20 A20 P25 N25
I/O O O O O
PUC PUB PDC PUC PUC
TC11IB
Table 1 Symbol CKE MR/W HOLD
Pin Definitions and Functions(cont'd) Pin P26 C21 C22 In PU/ Out PD1) O O I PUC PUC PUC Functions EBU_LMB SDRAM Clock Enable Output EBU_LMB Motorola-style Read / Write Output EBU_LMB Hold Request Input In External Master Mode: While HOLD is high, Tricore is operating in normal mode (is owner of the external bus). A high-to-low transition indicates a hold request from an external master.Tricore backs off the bus and activates HLDA and goes into hold mode. A low-to-high transitions causes an exit from hold mode.Tricore deactivates HLDA and takes over the bus and enters the normal operation again. In External Slave Mode: While both HOLD and HLDA are high, Tricore is in hold mode, the external bus interface signals are tristated. When Tricore is released out of hold mode (HLDA =0) and has completely taken over control of the external bus, a low level at this pin requests Tricore to go into hold mode again. But in any case Tricore will perform at least one external bus cycle before going into hold mode again. EBU_LMB Hold Acknowledge Input / Output In External Master Mode: OutPut. High during normal operation.When Tricore enters hold mode, it sets HLDA to low after releasing the bus. On exit of hold mode, Tricore first sets HLDA to high and then goes onto the bus again (to avoid collisions). In External Slave Mode: Input. A high-to-low transition at this pin releases Tricore from hold mode.
HLDA
A23
I/O
PUC
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol BREQ
Pin Definitions and Functions(cont'd) Pin B22 In PU/ Out PD1) O PUC Functions EBU_LMB Bus Request Output In External Master Mode: High during normal operation.Tricore activates BREQ earliest one clock cycle after activating HLDA, if it has to perform an external bus access. If Tricore has regained the bus, BREQ is set to high one clock cycle after deactivation of HLDA. In External Slave Mode: This signal is high as long as Tricore operates from internal memory. When it detects that an external access is required, it sets BREQ to low and waits for signal HLDA to become low. BREQ will go back to high when the slave has backed off the bus after it was requested to go into hold mode. EBU_LMB Read-Modify-Write Signal Line EBU_LMB Burst Address Advance Output For advancing address in a burst flash access EBU_LMB Burst Flash Address Valid Output EBU_LMB Additional Clock Output Additional clock running equal, 1/2, 1/3 or 1/4 frequency of EBUCLK EBU_LMB Command Delay Input For inserting delays between address and command. Test Mode Select Input For normal operation of the TC11IB, this pin should be connected to Vss. Test Mode Control Input 1 For normal operation of the TC11IB, this pin should be connected to VDDP. Test Mode Control Input 2 For normal operation of the TC11IB, this pin should be connected to VDDP.
RMW BAA ADV ACLK
AB23 A22 B19 M23
I/O O O O
PUC PUC PUC
CMDELA B21 Y TEST MODE TM CTRL1 TM CTRL2 AE9
I I
PUC PDC
C15
I
PUB
C12
I
PUB
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol CLK42
Pin Definitions and Functions(cont'd) Pin D12 In PU/ Out PD1) I PDC Functions Test Clock 42 MHz Input For normal operation of the TC11IB, this pin should be connected to Vss. Test PLL96 Analog Output For normal operation of the TC11IB, this pin must not be connected. Test PLL42 Analog Output For normal operation of the TC11IB, this pin must not be connected. Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the main oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the main oscillator amplifier circuit. For clocking the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. Main Oscillator Power Supply (1.8V) Main Oscillator Ground PLL96 Power Supply (1.8V) PLL96 Ground Test PLL42 Power Supply (1.8V) For normal operation of the TC11IB, this pin must not be connected. Test PLL42 Ground For normal operation of the TC11IB, this pin must be connected to Vss. LMU Reference Voltage This pin has to be connected to Vss ComDRAM Reference Voltage This pin has to be connected to Vss eDRAM Power Supply (1.8V)
PLL96 CTRL PLL42 CTRL XTAL1 XTAL2
B15
O
B12
O
A15 A14
I O

VDDOSC VSSOSC VDDPLL96 VSSPLL96 VDDPLL42
B14 C14 B13 A13 A12

VSSPLL42 C13
VLMUREF VCOMREF VDDDRAM
A16

AD10 A17, AF13
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) Functions Core and Logic Power Supply (1.8V)
VDD
H1 W1 T2,B4 B11 D6,F4 D10 D17 D21 F23 K4 K23 U4 U23 AA4 AA23 AC6 AC10 AC17 AC21
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol VDDP
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) Functions Ports Power Supply (3.3V)
D8, D11, D14, D16, D19, H4, H23, L4, L23, N4, P23, T4, T23, W4, W23, AC8, AC11, AC13, AC16, AC19
Data Sheet
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V2.3, 2003-11
TC11IB
Table 1 Symbol
Pin Definitions and Functions(cont'd) Pin In PU/ Out PD1) Functions Ground
VSS
D4 D9 D13 D18 D23 J4 J23 N23 P4,V4 V23 AC4 AC9 AC14 AC18 AC23 L11 to L16, M11 to M16, N11 to N16, P11 to P16, R11 to R16, T11 to T16 D15, A26, AE26, AF9, AF26
N.C.
Not Connected These pins must not be connected.
1) Refers to internal pull-up or pull-down device connected and corresponding type. The notation `' indicates that the internal pull-up or pull-down device is not enabled.
Data Sheet
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V2.3, 2003-11
TC11IB
Parallel Ports The TC11IB has 96 digital input/output port lines, which are organized into six parallel 16-bit ports, Port P0 to Port P5 with 3.3V nominal voltage. The digital parallel ports can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. An overview on the port-toperipheral unit assignment is shown in Figure 4.
A lte rn a te F u n ctio n s
G P IO
G P IO
A lte rn a te F u n ctio n s
G P T U 0 / G P T U 1 G P IO 0
G P IO 3 E xte rn a l In te rru p ts
TC11IB A S C / S S C / M M C I / 1 6 x5 0 G P IO 1 P a ra lle l P o rts G P IO 4 E xte rn a l In te rru p ts
E th e rn e t / M M C I G P IO 2
G P IO 5 M M C I
M C A 04951
Figure 4
Parallel Ports of the TC11IB
Data Sheet
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V2.3, 2003-11
TC11IB
Serial Interfaces The TC11IB includes three serial peripheral interface units: - Asynchronous/Synchronous Serial Interface (ASC) - High-Speed Synchronous Serial Interface (SSC) - Asynchronous Serial Interface (16X50) Asynchronous/Synchronous Serial Interface Figure 5 shows a global view of the functional blocks of the Asynchronous/Synchronous Serial interface ASC.
C lo c k C o n tro l
fASC
R xD A d d re s s D ecoder ASC M o d u le T xD P o rt C o n tro l
P 1 .6 / A S C _R xD P 1 .7 / A S C _ T xD
In te rru p t C o n tro l
M C B04938
Figure 5
General Block Diagram of the ASC Interfaces
ASC Module communicates with the external world via one pair of I/O lines. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC Module kernel. The Asynchronous/Synchronous Serial Interface provides serial communication between the TC11IB and other microcontrollers, microprocessors or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
Data Sheet
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V2.3, 2003-11
TC11IB
provides the ASC with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider. Features: * Full duplex asynchronous operating modes - 8- or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baudrate from 3 MBaud to 0.71 Baud (@ 48 MHz clock) * Multiprocessor mode for automatic address/data byte detection * Loop-back capability * Support for IrDA data transmission up to 115.2 KBaud maximum * Half-duplex 8-bit synchronous operating mode - Baudrate from 6 MBaud to 488.3 Baud (@ 48 MHz clock) * Double buffered transmitter/receiver * Interrupt generation - On a transmitter buffer empty condition - On a transmit last bit of a frame condition - On a receiver buffer full condition - On an error condition (frame, parity, overrun error) * FIFO - 8 bytes receive FIFO (RXFIFO) - 8 bytes transmit FIFO (TXFIFO) - Independent control of RXFIFO and TXFIFO - 9-bit FIFO data width - Programmable Receive/Transmit Interrupt Trigger Level - Receive and transmit FIFO filling level indication - Overrun error generation * Two pin pair RXD/TXD available at Port 1
Data Sheet
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TC11IB
High-Speed Synchronous Serial Interface Figure 6 shows a global view of the functional blocks of the High-Speed Synchronous Serial interface SSC.
Slave Master
C lo ck C o n tro l
fSSC R xD T xD R xD T xD S la ve M a ste r P o rt C o n tro l P 1 .2 / M T S R
A d d re ss D ecoder
SSC M o d u le
P 1 .1 / M R S T
SCLK
P 1 .0 / S C L K
In te rru p t C o n tro l
M C B 04 952
Figure 6
General Block Diagram of the SSC Interfaces
The SSC Module has three I/O lines, located at Port 1. The SSC Module is further supplied by separate clock control, interrupt control, address decoding, and port control logic. The SSC supports full-duplex and half-duplex serial synchronous communication up to 24 MBaud (@ 48 MHz module clock). The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal.
Data Sheet
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V2.3, 2003-11
TC11IB
Features: * Master and slave mode operation - Full-duplex or half-duplex operation * Flexible data format - Programmable number of data bits: 2 to 16 bit - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock * Baud rate generation from 24 MBaud to 366.2 Baud (@ 48 MHz module clock) * Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) * Three-pin interface - Flexible SSC pin configuration
Data Sheet
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V2.3, 2003-11
TC11IB
Asynchronous Serial Interface (16X50) The 16X50 is a universal asynchronous receiver/transmitter (UART) which is fully prorammable.It supports word lengths from five to eight bits, an optional parity bit and one or two stop bits.If enabled, the parity can be odd, even or forced to a defined state. The 16X50 includes a 16-bit programmable baud rate generator and an 8-bit scratch register, together with two 16-byte FIFOs -one for transmit and one for receive. It has six modem control lines and supports a diagnostic loop-back mode. An interrupt can be generated from any one of 10 sources. Figure 7 shows a global view of the functional blocks of the Asynchronous Serial Interface (16X50).
C lo ck C o n tro l
f 1 6 x5 0
P 1 .1 5 / 1 6 x5 0 _ R I P 1 .1 4 / 1 6 x5 0 _ C T S P 1 .1 3 / 1 6 x5 0 _ D T R
A d d re ss D e co d e r
1 6 x5 0 M o d u le
P o rt C o n tro l
P 1 .1 2 / 1 6 x5 0 _ D S R P 1 .1 1 / 1 6 x5 0 _ D C D P 1 .1 0 / 1 6 x5 0 _ R T S
In te rru p t C o n tro l
P 1 .9 / 1 6 x5 0 _ T xD P 1 .8 / 1 6 x5 0 _ R xD
M C B 0493 7
Figure 7
General Block Diagram of the 16X50 Interface
The 16X50 Module communicates with the external world via five input and three output lines located at Port 1. The 16X50 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The 16X50 represents such an integration with greatly enhanced features. The 16X50 is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 1 byte provided in the 16C450. The 16X50 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 16X50 by the larger transmit and receive
Data Sheet 30 V2.3, 2003-11
TC11IB
FIFO's. This allows the external processor to handle more networking tasks within a given time. The 4 selectable levels of FIFO trigger provided for maximum data throughput performance especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The 16X50 is capable of operation to 3 Mbps with a 48 MHz clock input (f16X50). Features: * * * * * * * * * * * Software upward compatible with the NS16550A Standard modem interface Programmable word length, stop bits and parity Programmable baud rate generator Interrupt generation Diagnostic loop-back mode Scratch register Automatic hardware/software flow control Programmable XON/XOFF characters Independent transmit and receive control FIFO - 16 byte transmit FIFO - 16 byte receive FIFO with error flags - Four selectable receive FIFO interrupt trigger levels
Data Sheet
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TC11IB
General Purpose Timer Units Figure 8 shows a global view of all functional blocks of the two General Purpose Timer Unit (GPTU0 & GPTU1) Modules.
IN 0 C lo c k C o n tro l fG PTU0 IN 1 IN 2 IN 3 IN 4 A d d re s s D ecoder GPTU0 M o d u le IN 5 IN 6 IN 7 SR0 SR1 SR2 In te rru p t C o n tro l SR3 SR4 SR5 SR6 SR7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 P 0 .5 / G P T U 0 _ IO 5 P 0 .6 / G P T U 0 _ IO 6 P 0 .7 / G P T U 0 _ IO 7 P o rt C o n tro l P 0 .0 / G P T U 0 _ IO 0 P 0 .1 / G P T U 0 _ IO 1 P 0 .2 / G P T U 0 _ IO 2 P 0 .3 / G P T U 0 _ IO 3 P 0 .4 / G P T U 0 _ IO 4
IN 0 C lo c k C o n tro l fG PTU1 IN 1 IN 2 IN 3 IN 4 A d d re s s D ecoder GPTU1 M o d u le IN 5 IN 6 IN 7 SR0 SR1 SR2 In te rru p t C o n tro l SR3 SR4 SR5 SR6 SR7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
M C B 04943
P 0 .8 / G P T U 1 _ IO 0 P 0 .9 / G P T U 1 _ IO 1 P 0 .1 0 / G P T U 1 _ IO 2 P o rt C o n tro l P 0 .1 1 / G P T U 1 _ IO 3 P 0 .1 2 / G P T U 1 _ IO 4 P 0 .1 3 / G P T U 1 _ IO 5 P 0 .1 4 / G P T U 1 _ IO 6 P 0 .1 5 / G P T U 1 _ IO 7
Figure 8
General Block Diagram of the GPTU Interface
Each GPTU module, GPTU0 and GPTU1, consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. And each GPTU module communicates with the external world via eight I/O lines located at Port 1.
Data Sheet
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TC11IB
The three timers in each GPTU Module T0, T1, and T2, can operate independently from each other or can be combined: General Features: * * * * All timers are 32-bit precision timers with a maximum input frequency of fGPTU. Events generated in T0 or T1 can be used to trigger actions in T2 Timer overflow or underflow in T2 can be used to clock either T0 or T1 T0 and T1 can be concatenated to form one 64-bit timer
Features of T0 and T1: * Each timer has a dedicated 32-bit reload register with automatic reload on overflow * Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers * Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events * Two input pins can determine a count option Features of T2: * Count up or down is selectable * Operating modes: - Timer - Counter - Quadrature counter (incremental/phase encoded counter interface) * Options: - External start/stop, one-shot operation, timer clear on external event - Count direction control through software or an external event - Two 32-bit reload/capture registers * Reload modes: - Reload on overflow or underflow - Reload on external event: positive transition, negative transition, or both transitions * Capture modes: - Capture on external event: positive transition, negative transition, or both transitions - Capture and clear timer on external event: positive transition, negative transition, or both transitions * Can be split into two 16-bit counter/timers * Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions. * Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins * T2 events are freely assignable to the service request nodes.
Data Sheet
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V2.3, 2003-11
TC11IB
MultiMediaCard Interface (MMCI) The MultiMediaCard Interface module provides interface to MultiMediaCard bus. It supports the full MultiMediaCard bus protocol as defined in MultiMediaCard system specification version 1.3. Figure 9 shows a global view of the MMCI module with the module specific interface connections.
C lock C ontrol
fM M CI
P 5.15 / M M C I_R O D P 5.2 / M M C I_C M D _R W P 5.0 / M M C I_D A T _R W
A ddre ss D ecoder
MMCI M odu le
P ort C ontrol
P 2.7 / M M C I_V D D E N P 1.5 / M M C I_D A T P 1.4 / M M C I_C M D
Interrupt C ontrol
P 1.3 / M M C I_C LK
M C B 04 946
Figure 9
General Block Diagram of MMCI Interface
The MMCI module communicates with external world via two IO lines and five output lines which are located at Port 1, 2 and 5. Clock control, interrupt service and address decoding are managed outside the MMCI module Kernel. MMCI handles the data transfer on CMD and DAT of the MMC Bus. It performs the transfer from bit serial to byte parallel or vice versa and sustains a 16Mbps data rate. To fulfil the MMC Bus protocol, special bytes are modified via inserting start and stop bits or CRC bits. A clock controller is implemented to divide the clock to the necessary MMC Bus clock frequency. Features * * * * * * * * * 3 line serial interface --- Glueless interface to MultiMediaCard Bus Pointer based data transfer Block and sequential card access 16MHz MultiMediaCard bus clock generation CRC protection for the MultiMediaCard bus communication Optional programming voltage control Buffered data transfer Power management Data communication with a data rate up to 2 Mbyte/s
Data Sheet
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TC11IB
Ethernet Controller The MAC controller implements the IEEE 802.3 and operates either at 100 Mbps or 10 Mbps. Figure 10 shows a global view of the Ethernet Controller module with the module specific interface connections.
E th e rne t C o n tro lle r
P 2 .1 5 / M II_ R xE R P 2 .1 4 / M II_ R xD [3 ] P 2 .1 3 / M II_ R xD [2 ] P 2 .1 2 / M II_ R xD [1 ] P 2 .1 1 / M II_ R xD [0 ] P 2 .1 0 / M II_ C O L RB P o rt C o n tro l
DMUR
P 2 .9 / M II_ C R S P 2 .8 / M II_ R xD V P 2 .6 / M II_ M D C MAC M II P 2 .5 / M II_ T xE N P 2 .4 / M II_ T xE R P 2 .3 / M II_ T xD [3 ]
FAST FPI (M /S )
DMUT
TB
P 2 .2 / M II_ T xD [2 ] P 2 .1 / M II_ T xD [1 ] P 2 .0 / M II_ T xD [0 ] M II_ T xC L K M II_ T xC L K M II_ T D IO
M C B 04942
Figure 10
General Block Diagram of the Ethernet Controller
The Ethernet controller comprises the following functional blocks: 1. 2. 3. 4. 5. Media Access Controller (MAC) Receive Buffer (RB) Transmit Buffer (TB) Data Management Unit in Receive Direction (DMUR) Data Management Unit in Transmit Direction (DMUT)
Data Sheet
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V2.3, 2003-11
TC11IB
RB as well as TB provides on-chip data buffering whereas DMUR and DMUT perform data transfer from/to the shared memory. Two interfaces are provided by the Ethernet Controller Module: 1. MII interface for connection of Ethernet PHYs via eighteen Input / Output lines 2. Master/slave FPI bus interface for connection to the on-chip system bus for data transfer as well as configuration. Features * * * * * * * Media Independent Interface (MII) according to IEEE 802.3 Support 10 or 100 Mbps MII-based Physical devices. Support Full Duplex Ethernet. Support data transfer between Ethernet Controller and COM-DRAM. Support data transfer between Ethernet Controller and SDRAM via EBU. 256 x 32 bit Receive buffer and Transmit buffer each. Support burst transfers up to 8 x 32 Byte.
Media Access Controller (MAC) * * * * * * * * * * * 100/10-Mbps operations Full IEEE 802.3 compliance Station management signaling Large on-chip CAM (Content Addressable Memory) Full duplex mode 80-byte transmit FIFO 16-byte receive FIFO PAUSE Operation Flexible MAC Control Support Support Long Packet Mode and Short Packet Mode PAD generation
Media Independent Interface (MII) * * * * * * * * * Media independence. Multi-vendor point of interoperability. Support connection of MAC layer and Physical (PHY) layer devices. Capable of supporting both 100 Mb/s and 10 Mb/s data rates. Data and delimiters are synchronous to clock references. Provides independent four bit wide transmit and receive data paths. Support connection of PHY layer and Station Management (STA) devices. Provides a simple management interface. Capable of driving a limited length of shielded cable.
Data Sheet
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V2.3, 2003-11
TC11IB
PCI The PCI Interface module of the TC11IB basically is a bus bridge between the on-chip FPI bus and the external PCI bus of the system. The PCI Interface is fully compliant to PCI Local Bus Specification Rev. 2.2. Figure 11 shows a global view of the PCI module with the module specific pin connections.
P _ A D [3 1 :0 ] P _ C /B E [3 :0 ] P_PAR P_SERR P_PERR P_STO P P_DEVSEL P_TRDY FAST FPI (M /S ) PCI M o d u le P_FRAM E P _ IR D Y P_LO CK P _ IN T A P _ IN T B P_PM E P_REQ P_G NT P _ ID S E L P_CLK33
M C B04949
Figure 11
General Block Diagram of the PCI Interface
The PCI-FPI bridge is able to execute a number of various data transfers between the FPI bus and the PCI bus. Beside the standard PCI functions (configuration transactions), there are two main types of transfers which the bridge supports. Firstly, it will forward a transaction that any PCI initiator directs to the PCI interface of the TC11IB to the on-chip FPI bus. Secondly the bridge will forward certain transactions that a FPI master initiates on the FPI bus to the PCI bus. Depending on configuration, these transfers may be a
Data Sheet 37 V2.3, 2003-11
TC11IB
single data or burst transfers on both PCI and FPI bus. In addition, the bridge is able to handle a direct data transfer between PCI bus and FPI bus utilizing it's programmable DMA channel. The DMA channel can only be activated by a FPI master. In order to work as a PCI host bridge on the PCI bus, the variety of PCI transactions issued by the bridge includes configuration transactions of type 0 and type 1 when acting as a PCI master. Features * PCI V2.2 compliant, 32 bit, 33 MHz * Multifunction Device, Support both PCI Master/Host functions. These functions can be activated by: - TriCore - Fast Ethernet - DMA Channel * Support Burst Transfer from PCI to ComDRAM, SDRAM and LMU. * Support DMA Channel data transfers between PCI and FPI * Loading of PCI Configuration Registers done by TriCore via FPI Bus access * Support PCI Command * Support Card-Bus. * Power management - according to PCI Bus Power Management Interface Specification V1.1 - Support Multiple PCI power management states D0, D1, D2, D3cold - PME#-Signalling from Fast Ethernet in D1, D2. * PCI Reset - All tristatable PCI outputs of the bridge are set to "Tristate" upon PCI Reset, compliant to PCI Local Bus Specification V2.2
Data Sheet
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V2.3, 2003-11
TC11IB
On-Chip Memories The TC11IB provides the following on-chip memories: * Program Memory Unit (PMU) with - 24 KBytes Scratch-pad Code RAM (SRAM) - 8 KBytes Instruction Cache Memory (I-CACHE) * Data Memory Unit (DMU) with - 24 KBytes Scratch-pad Data RAM (SRAM) - 8 KBytes Data Cache Memory (D-CACHE) * 16 KBytes Boot ROM (BROM) * eDRAM Local Memory Unit (LMU) with - 512 KBytes Code/Data Memory * ComDRAM with - 1MBytes Code/Data Memory * Peripheral Control Processor (PCP) with - 16 KBytes Data Memory (PCODE) - 4 KBytes Parameter RAM (PRAM)
Data Sheet
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V2.3, 2003-11
TC11IB
Address Map Table 2 defines the specific segment oriented address blocks of the TC11IB with its address range, size, and PMU/DMU access view. Table 3 shows the block address map of the Segment 15 which includes on-chip peripheral units and ports. Table 2 TC11IB Block Address Map Size 2 GB Description MMU/ FPI Space DMU Acc. PMU Acc. c a c h e d
Seg- Address ment Range 0 - 7 0000 0000H - 7FFF FFFFH 8 8000 0000H - 8FFF FFFFH 9 9000 0000H - 9FDF FFFFH 9FE0 0000H - 9FEF FFFFH 9FF0 0000H - 9FFF FFFFH 10
via via F_FPI F_ FPI via LMB via LMB
256 MB External Memory Space mapped from Segment 10 254 MB PCI Space mapped from Segment 11 1 MB 1 MB ComDRAM Space mapped from Segment 11 Reserved
via via F_FPI F_FPI - via LMB via LMB - - via LMB via LMB -
A000 0000H - 252 MB External Memory Space AFBF FFFFH AFC0 0000H - 512 KB LMU Space AFC7 FFFFH AFC8 0000H - AFFF FFFFH B000 0000H - BFDF FFFFH BFE0 0000H - BFEF FFFFH BFF0 0000H - BFFF FFFFH C000 0000H - C007 FFFFH C008 0000H - CFFF FFFFH 3.5 MB Reserved
254 MB PCI Space mappable into segment 9 1 MB 1 MB 512 KB 255.5 MB ComDRAM Space Reserved Local Memory Unit eDRAM Space Reserved
11
via via F_FPI F_FPI - via LMB - - via LMB -
n o nc a c h e d
12
c a c h e d
Data Sheet
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V2.3, 2003-11
TC11IB
Table 2
TC11IB Block Address Map(cont'd) Size 24 KB Description DMU Acc. PMU Acc. via LMB - PMU local -
Seg- Address ment Range D000 0000H - D000 5FFFH D000 6000H - D3FF FFFFH D400 0000H - D400 5FFFH D400 6000H - D7FF FFFFH D800 0000H - DDFF FFFFH DE00 0000H - DEFF FFFFH DF00 0000H - DFFF BFFFH
Local Data Scratchpad Memory DMU (SRAM) local - via LMB -
~ 64 MB Reserved 24 KB Local Code Scratchpad Memory (SRAM)
13
~64 MB Reserved 96 MB 16 MB External Memory Space Emulator Memory Space
via LMB -
via LMB - non-cached
~16 MB Reserved
DFFF C000H - 16 KB Boot ROM Space DFFF FFFFH E000 0000H - 128 MB External Memory Space E7FF FFFFH E800 0000H - E807 FFFFH E808 0000H - E83F FFFFH E840 0000H - E840 7FFFH E840 8000H - E84F FFFFH E850 0000H - E850 7FFFH E850 8000H - EFFF FFFFH 512 KB 3.5 MB 32 KB ~1 MB 32 KB ~123 MB Local Memory Space mapped to LMB Segment 12 Reserved
via via S_FPI S_FPI via LMB
14
- Local Data Memory (SRAM) mapped to LMB Segment 13 Reserved Local Code Memory (SRAM) mapped to LMB Segment 13 Reserved
-
Data Sheet
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TC11IB
Table 2
TC11IB Block Address Map(cont'd) Size 1 MB 512 KB 64 KB 2.4375 MB 1 MB Description On-Chip Peripherals & Ports Reserved ComDRAM Control Registers Reserved PCI/FPI-Bridge Registers DMU Acc. PMU Acc.
Seg- Address ment Range F000 0000H - F00F FFFFH F010 0000H - F017 FFFFH1) F018 0000H - F018 FFFFH F019 0000H - F03F FFFFH1) F040 0000H - F04F FFFFH 15 F050 0000H - F0FF FFFFH F100 0000H - F1FF FFFFH F200 0000H - F200 05FFH F200 0600H - F7E0 FEFFH F7E0 FF00H - F7E0 FFFFH F7E1 0000H - F7E1 FFFFH F7E2 0000H - F7FF FFFFH F800 0000H - F87F FFFFH F880 0000H - FFFF FFFFH
1)
via via S_FPI S_FPI - -
via via S_FPI S_FPI - via F_FPI - non-cached via F_FPI -
~11 MB Reserved 16 MB 6 x 256 B PCI Configuration Space BCU0 and Fast Ethernet Registers
-
~94 MB Reserved 256 B 64 KB
-
CPU Slave Interface Registers via (CPS) F_FPI Core SFRs - via LMB -
15 x 128 Reserved KB 8 MB LMB Peripheral Space (EBU_LMB and local memory eDRAM control registers)
120 MB Reserved
Any access to this area will result in unpredicted behaviors of PORTs.
Note: Accesses to address defined as "Reserved" in Table 2 lead to a bus error. The exceptions are marked with 1)
Data Sheet
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TC11IB
Table 3
Block Address Map of Segment 15 Address Range F000 0000H - F000 00FFH F000 0200H - F000 02FFH F000 0300H - F000 03FFH F000 0400H - F000 04FFH F000 0500H - F000 05FFH F000 0600H - F000 06FFH F000 0700H - F000 07FFH F000 0800H - F000 08FFH F000 0900H - F000 09FFH Size 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 256 Bytes 256 Bytes 256 Bytes 256 Bytes
Symbol Description SCU PCISIR BCU1 STM OCDS - GPTU0 GPTU1 ASC 16X50 SSC MMCI SRU - P0 P1 P2 P3 P4 P5 - PCP System Control Unit Slow FPI Bus Control Unit 1 System Timer On-Chip Debug Support Reserved General Purpose Timer Unit 0 General Purpose Timer Unit 1 Async./Sync. Serial Interface Asynchronous Serial Interface
PCI Software Interrupt Request F000 0100H - F000 01FFH
High-Speed Synchronous Serial F000 0A00H - F000 0AFFH Interface MultiMediaCard Interface Service Request Unit Reserved Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Reserved PCP Registers Reserved PCP Data Memory (PRAM) Reserved PCP Code Memory (PCODE) F000 0B00H - F000 0BFFH F000 0E00H - F000 27FFH F000 2800H - F000 28FFH F000 2900H - F000 29FFH F000 2A00H - F000 2AFFH F000 2B00H - F000 2BFFH
F000 0C00H - F000 0DFFH 512 Bytes
F000 2C00H - F000 2CFFH 256 Bytes F000 2D00H - F000 2DFFH 256 Bytes F000 2E00H - F000 3EFFH F000 3F00H - F000 3FFFH F000 4000H - F000 FFFFH F001 0000H - F001 0FFFH F001 1000H - F001 FFFFH F002 0000H - F002 3FFFH F002 4000H - F017 FFFFH F018 0000H - F018 FFFFH F019 0000H - F03F FFFFH
43
- 256 Bytes - 4 KBytes - 16 KBytes -1) 64 KBytes -1)
V2.3, 2003-11
- ComDRAM -
Reserved ComDRAM Control Registers Reserved
Data Sheet
TC11IB
Table 3
Block Address Map of Segment 15(cont'd) Address Range F040 0000H - F04F FFFFH F050 0000H - F0FF FFFFH F100 0000H - F1FF FFFFH F200 0000H - F200 00FFH F200 0100H - F200 05FFH F200 0600H - F7E0 FEFFH F7E1 0000H - F7E1 7FFFH F7E1 8000H - F7E1 80FFH Size 1 MBytes - 16 MBytes 256 Bytes 1280 Bytes - - 256 BYTES
Symbol Description PCI - PCI Bridge Configuration Registers Reserved
PCI_CS PCI Configuration Space x(x=1,2) Registers BCU0 ECU - CPU Fast FPI Bus Control Unit 0 Ethernet Controller Unit Reserved Reserved MMU Reserved Memory Protection Registers Reserved Core Debug Register (OCDS)
Slave Interface Registers (CPS) F7E0 FF00H - F7E0 FFFFH 256 Bytes
F7E1 8100H - F7E1 BFFFH - F7E1 C000H - F7E1 EFFFH 12 KBytes F7E1 F000H - F7E1 FCFFH - F7E1 FD00H - F7E1 FDFFH 256 Bytes
Core Special Function Registers F7E1 FE00H - F7E1 FEFFH 256 Bytes (CSFRs) General Purpose Register (GPRs) - EBU - LMU - DMU PMU LCU LFI -
1)
F7E1 FF00H - F7E1 FFFFH 256 Bytes F7E2 0000H - F7FF FFFFH - F800 0000H - F800 01FFH F800 0200H - F800 03FFH F800 0400H - F800 04FFH F800 0500H - F87F FBFFH 512 Bytes - 256 Bytes -
Reserved EBU_LMB External Bus Unit Reserved Local Memory Unit Reserved Local Data Memory Unit Local Program Memory Unit LMB Bus Control Unit LMB to FPI Bus Bridge (LFI) Reserved
F87F FC00H - F87F FCFFH 256 Bytes F87F FD00H - F87F FDFFH 256 Bytes F87F FE00H - F87F FEFFH 256 Bytes F87F FF00H - F87F FFFFH F880 0000H - FFFF FFFFH 256 Bytes -
Any access to this area will result in unpredicted behaviors of PORTs.
Data Sheet
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TC11IB
Note: Accesses to address defined as "Reserved" in Table 3 lead to a bus error.The exceptions are marked with 1) Memory Protection System The TC11IB memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. In SAF-T11IB-64D96, TriCore supports two address spaces: The virtual address space and The physical address space. Both address space are 4GB in size and divided into 16 segments with each segment being 256MB. The upper 4 bits of the 32-bit address are used to identify the segment. Virtual segments are numbered 0 - 15. But a virtual address is always translated into a physical address before accessing memory. The virtual address is translated into a physical address using one of two translation mechanisms: (a) direct translation, and (b) Page Table Entry (PTE) based translation. If the virtual address belongs to the upper half of the virtual address space then the virtual address is directly used as the physical address (direct translation). If the virtual address belongs to the lower half of the address space, then the virtual address is used directly as the physical address if the processor is operating in Physical mode (direct translation) or translated using a Page Table Entry if the processor is operating in Virtual mode (PTE translation). These are managed by Memory Management Unit (MMU) Memory protection is enforced using separate mechanisms for the two translation paths. Protection for direct translation Memory protection for addresses that undergo direct translation is enforced using the range based protection that has been used in the previous generation of the TriCore architecture. The range based protection mechanism provides support for protecting memory ranges from unauthorized read, write, or instruction fetch accesses. The TriCore architecture provides up to four protection register sets with the PSW.PRS field controlling the selection of the protection register set. Because the TC11IB uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes.
Data Sheet
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TC11IB
Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes which apply to the specified range. Protection for PTE based translation Memory protection for addresses that undergo PTE based translation is enforced using the PTE used for the address translation. The PTE provides support for protecting a process from unauthorized read, write, or instruction fetches by other processes. The PTE has the following bits that are provided for the purpose of protection: l XE (Execute Enable) enables instruction fetch to the page. l WE (Write Enable) enables data writes to the page. l RE (Read Enable) enables data reads from the page. Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual address space are disallowed when operating in Virtual mode. In Physical mode, User0 accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual address that is restricted to User-1 or Super-visor mode will cause a Virtual Address Protection (VAP) Trap in both the Physical and Virtual modes.
Data Sheet
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TC11IB
On-Chip Bus System The TC11IB includes two bus systems: - Local Memory Bus (LMB) - On-Chip FPI Bus (Fast FPI and Slow FPI) There are two bridges to interconnect these three buses. The LMB-to-FPI (LFI) interfaces the Fast FPI bus to LMB Bus. The FPI-to-FPI (FFI) interfaces slow FPI bus to Fast FPI bus. Local Memory Bus (LMB) The Local Memory Bus interconnects the memory units and functional units, such as CPU and LMU. The main target of the LMB bus is to support devices with fast response times, optimized for speed. This allows the DMU and PMU fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. Via External Bus Unit, it interconnects TC11IB and external components. The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. It supports 8,16,32 & 64 bits single beat transactions and variable length 64 bits block transfers. Key Features The LMB provides the following features: * * * * * * Synchronous, Pipelined, Multi-master, 64-bit high performance bus Support multiple bus masters Support Split transactions Support Variable block size transfer Burst Mode Read/Write to Memories Connect Caches and on-chip memory and Fast FPI Bus
Data Sheet
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TC11IB
On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC11IB, such as the PCP and onchip peripheral components. The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 800 MBytes/s can be achieved with a 100 MHz bus clock and 32bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Via External Bus Unit (EBU), FPI Bus also interconnects the external components to TC11IB. There are two FPI buses in TC11IB, Fast FPI Bus and Slow FPI Bus. In order to improve the system performance, the peripherals are splitted into two FPI buses based on their performance. The fast FPI bus runs at a speed of 96 MHz where most of the high performance peripheral like ComDRAM, PCI-FPI, Ethernet Controller, LFI etc. are connected. The slow FPI bus runs at half speed of its fast counter part. And it is used to connect some standard peripherals. There is a FPI-FPI bridge between them to transfer data. Each of FPI buses has its own Bus Control Unit (BCU). Features * * * * * * * * Supports multiple bus masters Supports demultiplexed address/data operation Address bus up to 32 bits and data buses are 64 bits wide Data transfer types include 8-, 16-, 32- and 64 bit sizes Supports Burst transfer Single- and multiple-data transfers per bus acquisition cycle Designed to minimize EMI and power consumption Controlled by an Bus Control Unit (BCU) - Arbitration of FPI Bus master requests - Handling of bus error.
FFI-Bridge Features * * * * * Supports Single/Block* Data Read/Write Transactions (8/16/32 Bit) Supports FPI- Read Modify Write Transactions (RMW) Internal FIFO Interfaces between FPI master and FPI slave. Optimized for FPI-Bus frequency ratios 2:1 Special Retry/Abort functionality
Note: Block Transaction support depends on generic settings and the depth of the bridge internal read- and write data buffer.
Data Sheet
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TC11IB
LFI The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI bus to the Local Memory Bus (LMB). LFI Features * * * * Compatible with the FPI 3.2 and LMB bus Specification V2.4 Supports Burst/Single transactions, from FPI to LMB. Supports Burst/Single transactions, from LMB to FPI High efficiency and performance: - fastest access across the bridge takes three cycles, using a bypass. - There are no dead cycles on arbitration. Acts as the default master on FPI side. Supports abort, error and retry conditions on both sides of the bridge. Supports FPI's clock the same, or half, as the LMB's clock frequency. LMB clock is shut when no transactions are issue to LFI from both buses and none are in process in the LFI to minimize the power consumption.
* * * *
Data Sheet
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V2.3, 2003-11
TC11IB
LMB External Bus Unit The LMB External Bus Control Unit (EBU_LMB) of the TC11IB is the interface between external resources, like memories and peripheral units, and the internal resources connected to on-chip buses if enabled. The basic structure and external interconnections of the EBU are shown in Figure 12.
32 4 24
A D [3 1 :0 ] B C [3 :0 ] A [2 3 :0 ] RD
PMU
LM U
R D /W R W A IT SVM
T riC o re
MMU
LM B
H LD A BREQ ALE
DMU
LFI
RAS 7 C S [6 :0 ] CSEM U EBU _LM B
FAST FPI
C SG LB CSOVL
T o P e rip h e ra ls
CAS CKE
FFI
M R /W RMW H O LD
SLO W FPI
CSFPI EBU C LK
T o P e rip h e ra ls and P C P
BAA ADV AC LK C M D ELAY
M C B 04941
Figure 12
EBU Structure and Interfaces
Data Sheet
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V2.3, 2003-11
TC11IB
The EBU is mainly used for the following two operations: * Masters on LMB bus access external memories through EBU_LMB * An external (off-chip) master access internal (on-chip) devices through FPI Bus. The EBU controls all transactions required for these two operations and in particular handles the arbitration of the external bus between multi-masters. The types of external resources accessed by the EBU are: * * * * * * * INTEL style peripherals (separate RD and WR signals) Motorola style peripherals (MR/ W signals) ROMs, EPROMs Static RAMs PC 100 SDRAMs (Burst Read/Write Capacity / Multi-Bank/Page support) Specific types of Burst Mode Flashes (Intel 28F800F3/28F160F3, AMD 29BL162) Special support for external emulator/debug hardware
Features * Support Local Memory Bus (LMB 64-bit) * Support External bus frequency up to 96 MHz and internal LMB frequency up to 166 MHz. External bus frequency: LMB frequency =1:1 or 1:2 or 1:4 * Highly programmable access parameters * Support Intel-and Motorola-style peripherals/devices * Support PC 100 SDRAM (burst access, multibanking, precharge, refresh) * Support 16-and 32-bit SDRAM data bus and 64,128 and 256MBit devices * Support Burst flash (Intel 28F800F3/160F3,AMD 29BL162) * Support Multiplexed access (address &data on the same bus) when PC 100 SDRAM is not implemented * Support Address Alignment, external address space up to 64 MBytes. * Support Data Buffering: Code Prefetch Buffer, Read/Write Buffer. * External master arbitration compatible to C166 and other Tricore devices * 8 programmable address regions (1 dedicated for emulator) * Support Little-and Big-endian * Signal for controlling data flow of slow-memory buffer * Slave unit for external (off-chip) master to access devices on FPI bus
Data Sheet
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TC11IB
Peripheral Control Processor The Peripheral Control Processor (PCP) performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor's first line of defense as an interrupt-handling engine. The PCP can offload the CPU from having to service time-critical interrupts. This provides many benefits, including: * Avoiding large interrupt-driven task context-switching latencies in the host processor * Lessening the cost of interrupts in terms of processor register and memory overhead * Improving the responsiveness of interrupt service routines to data-capture and datatransfer operations * Easing the implementation of multitasking operating systems. The PCP has an architecture which efficiently supports DMA type transactions to and from arbitrary devices and memory addresses within the TC11IB and also has reasonable stand alone computational capabilities. The PCP is made up of several modular blocks as follows: * * * * * * PCP Processor Core Code Memory (PCODE) Parameter Memory (PRAM) PCP Interrupt Control Unit (PICU) PCP Service Request Nodes (PSRN) System bus interface to the slow FPI Bus
The PCP is fully interrupt-driven, meaning it is only activated through service requests; there is no main program running in the background as with a conventional processor.
Data Sheet
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TC11IB
C ode M e m o ry PCODE
P a ra m e te r M e m o ry PRAM
PCP P ro c e s s o r C o re
F P I-In te rfa c e
P C P S e rv ic e R eq. N odes PSRNs
P C P In te rru p t C o n tro l U n it P IC U
FPI Bus
P C P In te rru p t A rb itra tio n B u s C P U In te rru p t A rb itra tio n B u s
M C B04784
Figure 13 Table 4
PCP Block Diagram PCP Instruction Set Overview Description Efficient DMA channel implementation Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Add, subtract, compare and complement Divide and multiply And, Or, Exclusive Or, Negate, MCLR and MSET Shift right or left, rotate right or left, prioritize Set, clear, insert and test bits jump conditionally, jump long, exit, No operation Debug
Instruction Group DMA primitives Load/Store
Arithmetic Divide/Multiply Logical Shift Bit Manipulation Flow Control Miscellaneous
Data Sheet
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TC11IB
System Timer The STM within the TC11IB is designed for global system timing applications requiring both high precision and long range. The STM provides the following features: * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Driven by clock, fSTM (identical with the system clock fSYS = 48MHz). Counting begins at power-on reset Continuous operation is not affected by any reset condition except power-on reset
The STM is an upward counter, running with the system clock frequency. It is enabled per default after reset, and immediately starts counting up. Other than via reset, it is no possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. The maximum clock period is 256 x fSTM. At fSTM = 48 MHz, for example, the STM counts 47.6 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflow.
STM M odule
fSTM
PORST
55
47
39
31
23
15
7
5 6-B it S yste m T im e r
C lo ck C o ntrol
E na b le / D isab le
00 H 00 H T IM 5
CAP T IM 6
A d d re ss D e co de r
T IM 4 T IM 3 T IM 2 T IM 1 T IM 0
M C A 04795
Figure 14
Block Diagram of the STM Module
Data Sheet
54
V2.3, 2003-11
TC11IB
Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC11IB in a user-specified time period. When enabled, the WDT will cause the TC11IB system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC11IB system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard "Watchdog" function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT control register, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). A further enhancement in the TC11IB's Watchdog Timer is its reset prewarning operation. Instead of immediately resetting the device on the detection of an error, as known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. Features * 16-bit Watchdog counter * Selectable input frequency: fSYS/256 or fSYS/16384 (fSYS = 48MHz) * 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes * Incorporation of the ENDINIT bit and monitoring of its modifications * Sophisticated password access mechanism with fixed and user-definable password fields * Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited. * Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation. * Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. * Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. * Double Reset Detection: If a Watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC11IB is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
Data Sheet
55
V2.3, 2003-11
TC11IB
* Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. System Control Unit The System Control Unit (SCU) of the TC11IB handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are: * PLL Control - PLL_CLC Clock Control Register - fSYS = 96MHz clock generation. - fSYS = 48MHz clock generation. * Reset Control - Generation of all internal reset signals - Generation of external HDRST reset signal - Generation of LMU eDRAM reset signals * Boot Scheme - Hardware Booting Scheme - Software Booting Scheme * Power Management Control - Enabling of several power-down modes - Control of the PLL in power-down modes * Watchdog Timer * OCDS2 Trace Port Control * Selection between PCI and Cardbus (PCMCIA) Standard Compliance * FFI Bridge Control * Device Identification Registers
Data Sheet
56
V2.3, 2003-11
TC11IB
Interrupt System An interrupt request can be serviced either by the CPU or by the Peripheral Control Processor (PCP). These units are called "Service Providers". Interrupt requests are called "Service Requests" rather than "Interrupt Requests" in this document because they can be serviced by either of the Service Providers. Each peripheral in the TC11IB can generate service requests. Additionally, the Bus Control Unit, the Debug Unit, the PCP, and even the CPU itself can generate service requests to either of the two Service Providers. As shown in Figure 15, each TC11IB unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where "mod" is the identifier of the service requesting unit and "x" an optional index. Two buses connect the SRNs with two Interrupt Control Units, which handle interrupt arbitration among competing interrupt service requests, as follows: * The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus. * The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP and administers the PCP Interrupt Arbitration Bus. Units which can generate service requests are: - - - - - - - - - - - - General Purpose Timer Units (GPTU 0 and GPTU 1) with 8 SRNs each High-Speed Synchronous Serial Interfaces (SSC) with 3 SRNs Asynchronous/Synchronous Serial Interfaces (ASC) with 4 SRNs Asynchronous Serial Interface (16X50) with 1 SRN PCI with 33 SRNs Ethernet Controller with 9 SRNs MultiMediaCard (MMCI) with 1 SRN External Interrupts with 24 SRNs Bus Control Units (BCU0 and BCU1) with 1 SRN each Peripheral Control Processor (PCP) with 12 SRNs Central Processing Unit (CPU) with 4 SRNs Debug Unit (OCDS) with 1 SRN
The PCP can make service requests directly to itself (via the PICU), or it can make service requests to the CPU. The Debug Unit can generate service requests to the PCP or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can make service requests to the PCP. The CPU Service Request Nodes are activated through software.
Data Sheet
57
V2.3, 2003-11
TC11IB
PCP In te rru p t A rb itra tio n B u s S e rvice R e q u e sto rs GPTU0 GPTU1 SSC ASC 16x50 PCI E th e rn e t MMCI E x te rn a l BCU0 BCU1 OCDS 8 8 3 4 1 33 9 1 24 1 1 1 S e rvice R e q u e st Nodes 8 SRNs 8 SRNs 3 SRNs 4 SRNs 1 SRN 33 SRNs 9 SRNs 1 SRN 24 SRNs 1 SRN 1 SRN 1 SRN
CPU In te rru p t A rb itra tio n B u s In te rru p t C o n tro l U n its In te rru p t S e rvice P ro vid e rs In t. A c k. CCPN 2 PC P 2 5 3
8 8 8 8 3 3 4 4 1 1 33 33 9 9 1 1 24 24 1 1 1 1 1 1 P IP N IC U In t. R e q . 4 4 4 SRNs 4 2 2 5 5 3 5 SRNs 3 SRNs In t. R e q . P IP N PIC U 2 SRNs 2 SRNs
S o ftw a re In te rru p t
C PU In t. A c k. CCPN
M C B 049 44
Figure 15
Block Diagram of the TC11IB Interrupt System
Data Sheet
58
V2.3, 2003-11
TC11IB
Boot Options The TC11IB booting schemes provides a number of different boot options for the start of code execution. Table 5 shows the boot options available in the TC11IB. Table 5 Boot Selections Type of Boot Start directly in core scratchpad memory Start from Boot ROM Boot Source Initial PC Value SRAM (Only via SW Reset) Boot ROM, SSC BSL mode1) (BootStrap Loader) or ASC BSL mode1) D400 0000H
OCDSE BRKIN CFG CFG [3] [2:0] 1 1 X 000B
Not (000 or 100)
DFFF FFFCH
0 1
100B 100B
A000 0000H External memory as External slave directly via EBU Memory (non-cached, External memory as CS0) master directly via EBU Tri-state chip (deep sleep) Go to halt with EBU enabled as slave Go to halt with EBU enabled as master Go to halt with EBU disabled Go to external emulator space - DE00 0000H - - - -
1 0
0 1
don't care 0 1 all other combinations 100B
0
0
don't care
1) SSC/ASC BootStrap Loader is built in BOOT ROM which provides a mechanism to load the startup program, which is executed after reset, via the SSC/ASC interface. After successfully loaded, the startup program will be executed from the address at 0xC000 0004H.
Data Sheet
59
V2.3, 2003-11
TC11IB
Power Management System The TC11IB power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are four power management modes: * * * * Run Mode Idle Mode Sleep Mode Deep Sleep Mode Power Management Mode Summary Description The system is fully operational. All clocks and peripherals are enabled, as determined by software. The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. The system clock continues to be distributed only to those peripherals programmed to operate in Sleep Mode. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine. The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM).
Table 6 describes these features of the power management modes. Table 6 Mode Run Idle
Sleep
Deep Sleep
Besides these explicit software-controlled power-saving modes, TC11IB supports automatic power-saving in that operating units, which are currently not required or idle, are shut off automatically until their operation is required again.
Data Sheet
60
V2.3, 2003-11
TC11IB
On-Chip Debug Support The On-Chip Debug Support of the TC11IB consists of four building blocks: * OCDS module in the TriCore CPU - On-chip breakpoint hardware - Support of an external break signal * OCDS module in the PCP - Special DEBUG instruction for program execution tracing * Trace module of the TriCore - Outputs 16 bits per cycle with pipeline status information, PC bus information, and breakpoint qualification information * Debugger Interface (Cerberus) - Provided for debug purposes of emulation tool vendors - Accessible through a JTAG standard interface with dedicated JTAG port pins Figure 16 shows a basic block diagram of the building blocks.
.
FPI Bus
B R K IN PC P SC U OCDS T ra c e C o n tro l 16 TriC ore C PU OCDS OCDSE BRKOUT
OCDS2
O C D S 2 [1 5 :0 ]
TDI TDO C erberus & JTA G TM S TCK TRST
M C B04947
JT A G I/O L in e s
Figure 16
Data Sheet
OCDS Support Basic Block Diagram
61 V2.3, 2003-11
TC11IB
Clock Generation Unit The Clock Generation Unit in the TC11IB, shown in Figure 17, consists of an oscillator circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it losses the lock on the external clock. PLL can provide the 96MHz and 48MHz clocks. In general, the Clock Generation Unit (CGU) is controlled through the System Control Unit (SCU) module of the TC11IB.
C lock G eneration U nit CGU XTAL1 O scilla to r f O S C C ircu it XTAL2 N D ivid e r PLL K :2 D ivid e r 1 MUX 0 S yste m _ CLK fSYS = 48 M Hz >1 fVCO VCO 1 MUX 0 K :1 D ivid e r 1 MUX 0 S yste m _ CLK fSYS = 96 M Hz
P h a se D e te ct.
L o ck D e te cto r
O S C _ F A IL
PLL D e e p N D IV V C O _ V C O _ K D IV P L L _ P L L _ P L L _ L o cke d S le e p [5 :0 ] S E L B Y P A S S [3 :0 ] 2 E N 2 S E L B Y P A S S [1 :0 ] R e g iste r P L L _ C L C
System C ontrol U nit SC U
M C A 0494 0
Figure 17
Clock Generation Unit Block Diagram
Data Sheet
62
V2.3, 2003-11
TC11IB
Recommended Oscillator Circuits
V DDOSC V DDOSC
XTAL1 12 MHz TC 11IB O s c illa to r XTAL2
E x te rn a l C lo c k S ig n a l
XTAL1 TC 11IB O s c illa to r XTAL2
C1
C2
V SSOSC
V SSOSC
M C S 04948
Figure 18
Oscillator Circuitries
For the main oscillator of the TC11IB the following external passive components are recommended: - Crystal: 12 MHz - C1, C2: 10 pF A block capacitor between VDDOSC and VSSOSC is recommended, too.
Data Sheet
63
V2.3, 2003-11
TC11IB
Power Supply The TC11IB provides an ingenious power supply concept in order to improve the EMI behavior as well as to minimize the crosstalk within on-chip modules. Figure 19 shows the TC11IB's power supply concept, where certain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling.
V S S (1 .8 V ) V DD
V SS V DDDRAM
V SS V LM UREF
PCP M e m o ry
DMU
PMU
CPU & P e rip h e ra l L o g ic
LM U
Com DRAM
PCI P o rts
G P IO P o rts (P 0 -P 5 )
EBU P o rts
PLL
OSC
V DDDRAM V CO MREF V SS V SS
V D D P (3 .3 V ) V SS
V DDPLL96 V SSPLL96
V DDOSC V SSOSC
M C B04953
Figure 19
TC11IB Power Supply Concept
Data Sheet
64
V2.3, 2003-11
TC11IB
Power Sequencing During power-up, the reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. While powering up (rising of the supply voltages from 0V to their regular operating values), it has to be ensured, that the core power supply VDD reaches its operating value first, and then the GPIO power supply VDDP. During the rising time of the core power supply it must be ensured that 0 < VDD - VDDP < 0.5V. During power-down, the core and GPIO power supplies VDD and VDDP respectively, have to be switched off completely until all capacitances are discharged to zero, before the next power-up. Note: The state of the pins are undefined when only the port voltage VDDP is switched on.
Data Sheet
65
V2.3, 2003-11
TC11IB
Identification Register Values Table 7 TC11IB Identification Registers Short Name SCU_ID MANID CHIPID RTID BCU1_ID STM_ID JPD_ID GPTU0_ID GPTU1_ID ASC_ID 16X50_ID SSC_ID MMCI_ID PCP_ID PCI_ID PCI_SUBID PCI_CS1_ID PCI_CS1_SUBID PCI_CS2_ID PCI_CS2_SUBID BCU0_ID CPU_ID MMU_ID EBU_ID LMU_ID DMU_ID PMU_ID LCU_ID LFI_ID Address F000 0008H F000 0070H F000 0074H F000 0078H F000 0208H F000 0308H F000 0408H F000 0608H F000 0708H F000 0808H F000 0908H F000 0A08H F000 0B08H F000 3F08H F040 0034H F040 0038H F100 0000H F100 002CH F100 0100H F100 012CH F200 0008H F7E0 FF18H F7E1 8008H F800 0008H F800 0410H F87F FC08H F87F FD08H F87F FE08H F87F FF08H Value 0013 C002H 0000 1820H 0000 8502H 0000 0000H 0000 6A06H 0000 C002H 0000 6302H 0001 C002H 0001 C002H 0000 4461H 0012 C001H 0000 4503H 0000 5B01H 0020 C002H 0001 15D1H 0000 15D1H 0001 15D1H 0001 15D1H 0001 15D1H 0002 15D1H 0000 6A06H 0015 C004H 0009 C002H 0014 C003H 0016 C001H 0008 C002H 000B C002H 000F C003H 000C C003H
Data Sheet
66
V2.3, 2003-11
TC11IB
Absolute Maximum Ratings Parameter Ambient temperature Symbol -25 -65 - -0.5 -0.3 -0.3 -0.3 Limit Values min. max. 85 150 110 4.5 2.4 2.4 2.4 C C C V V V V under bias under bias Unit Notes
TA TST Storage temperature Junction temperature TJ Voltage on I/O Supply pins with VDDP
respect to ground (VSS) Voltage on Core Supply pins with respect to ground (VSS) Voltage on PLL Supply pins with respect to ground (VSS) Voltage on Oscillator Supply pins with respect to ground (VSS)
VDD VDDPLL VDDOSC
Voltage on eDRAM Supply pins VDDDRAM -0.3 with respect to ground (VSS) Voltage on any pin with respect VIN to ground (VSS) Input current on any pin during IIN overload condition Absolute sum of all input currents during overload condition Power dissipation IIN -0.5 -10 -
2.4 4.5 10 |100|
V V mA mA
PDISS
-
1.6
W
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN>VDD or VINData Sheet
67
V2.3, 2003-11
TC11IB
Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC11IB. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Parameter Supply voltage Symbol Limit Values min. max. 3.6 1.89 1.89 1.89 1.89 0 -25 - - 85 96 50 V V V V V V C MHz pF I/O supply Core supply PLL supply Oscillator supply eDRAM supply 3.0 1.71 1.71 1.71 1.71 Unit Notes
Ground voltage Ambient temperature under bias CPU clock External Load Capacitance Parameter Interpretation
VDDP VDD VDDPLL VDDOSC VDDDRAM VSS TA fCPU CL
The parameters listed in the following partly represent the characteristics of the TC11IB and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the TC11IB will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the TC11IB.
Data Sheet
68
V2.3, 2003-11
TC11IB
DC Characteristics
DC-Characteristics VSS = 0 V; TA = -25 C to +85 C Parameter Symbol Limit Values min. GPIO pins, Dedicated pins and EBU pins Input low voltage Input high voltage Output low voltage Output high voltage Pull-up current 1) Pull-down current 2) Input leakage current 3) Pin Capacitance 4) max. Unit Test Condition
VIL VIH VOL VOH IPUB IPUC IPDA IPDC IOZ2 CIO
SR SR CC CC CC CC CC CC CC CC
- 2.0 - 2.4 -37 -12 55 2 - -
0.8 - 0.4 - -12 -2 220 14 1 10
V V V V A A A A A pF
VIN = 0V VIN = 0V VIN = VDDP VIN = VDDP 0 < VIN < VDDP
PCI pins Input low voltage Input high voltage Output low voltage Output high voltage Input Pull-up voltage 5) Input leakage current 6) PME input leakage 7)
VILP SR -0.5 VIHP SR 0.5VDDP VOLP CC VOHP CC VIPU CC IIL CC IOFF CC
- 0.9VDDP 0.7VDDP - -
0.3VDDP
V V V V A A
VDDP +
0.5 0.1VDDP - - 10 1
IOLP = 1500A IOHP = -500A
0 < VIN < VDDP
VIN 3.6V VDD off or
floating
Input pin capacitance 8) CLK pin capacitance
CIN CC - CCLK CC 5
10 12
pF pF
Data Sheet
69
V2.3, 2003-11
TC11IB
DC-Characteristics(cont'd) VSS = 0 V; TA = -25 C to +85 C Parameter IDSEL pin capacitance Pin inductance
9)
Symbol
Limit Values min. max. 8 20
Unit Test Condition pF nH
CIDSELCC - LPIN CC -
Oscillator Pins Input low voltage at XTAL1
VILX SR
-0.3 0.7 x VDDOSC
0.3 x VDDOSC 2.4
V V
Input high voltage at XTAL1 VIHX SR
Notes:
1)
The current is applicable to the pins, for which a pull up has been specified. Refer to Table 1. IPUx refers to the pull up current for type x. The current is applicable to the pins, for which a pull down has been specified. Refer to Table 1. IPDx refers to the pull down current for type x. Pins with internal pull up or pull down are not included. Not 100% tested, guaranteed by design characterization. This specification is guaranteed by design. It is the minimum voltage to which pull up resistors are calculated to pull a floated network. Applications sensitive to static power utilization must assure that the input buffer is conducting minimum current at this input voltage. Input leakage currents include high impedance output leakage for all bi-directional buffers with tristate outputs. This input leakage is the maximum allowable leakage into the PME open drain driver when power is removed from VDD of the component. This assumes that no event has occurred to cause the device to attempt to assert PME. Absolute maximum pin capacitance for a PCI input is 10pF (except for CLK). Exceptions are granted to motherboard-only devices up to 16pF. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
2)
3) 4) 5)
6) 7)
8)
9)
Data Sheet
70
V2.3, 2003-11
TC11IB
Power Supply Current
Parameter Active mode supply current
Symbol
Limit values typ. 1) max. 629 519 60 50 308 259 20 29 288 239 20 29 69 41 10 18 481.9 412.9 44.0 25.0
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Test Conditions Sum of IDDS 2)
IDD
Idle mode supply current
IID
213.0 195.8 6.5 10.7
Sleep mode supply current
ISL
195.4 178.2 6.5 10.7
IDD at VDD 3) IDD at VDDP IDD at VDDDRAM Sum of IDDS2)4) IDD at VDD3)4) IDD at VDDP4) IDD at VDDDRAM4) Sum of IDDS2)5)6) IDD at VDD3)5)6) IDD at VDDP5)6) IDD at VDDDRAM5)6) Sum of IDDS2)7) IDD at VDD3)7) IDD at VDDP7) IDD at VDDDRAM7)
Deep sleep mode supply current
IDS
11.2 6.7 0.3 4.2
1)
Typical values are measured at 25C, CPU clock at 96MHz and nominal supply voltage, i.e. 3.3V for VDDP and 1.8V for VDD, VDDPLL, VDDOSC and VDDDRAM. These currents are measured using a typical application pattern. The power consumption of modules can increase or decrease using other application programs. The PLL is bypassed while PCI and MMCI modules are inactive. These power supply currents are defined as the sum of all currents at the VDD power supply lines: VDD + VDDP + VDDDRAM + VDDPLL + VDDOSC This measurement includes the TriCore and Logic power supply lines. CPU is in idle state, input clock to all peripherals are enabled, Input clock to all peripherals are disabled. The values are not subject to production test - verified by characterization only. Clock generation is disabled at the source.
2)
3) 4) 5) 6) 7)
Data Sheet
71
V2.3, 2003-11
TC11IB
AC Characteristics (Operating Conditions apply)
2.4V 2.0V test points 0.8V 0.4V 0.8V 2.0V
AC inputs during testing are driven at 2.4V for a logic "1" and 0.4V for a logic "0". Timing measurements are made at VIHmin for a logic "1" and VILmax for a logic "0".
Figure 20
Input/Output Waveforms for AC Tests - for GPIO, Dedicated and EBU pins
Data Sheet
72
V2.3, 2003-11
TC11IB
Input Clock Timing (Operating Conditions apply) Parameter Oscillator clock frequency Input clock frequency driving at XTAL1 Input Clock high time Input Clock low time Input Clock rise time Input Clock fall time with PLL with PLL Symbol Limits min max 12 12 - - 4.1 4.1 MHz MHz ns ns ns ns Unit
fOSC SR fOSCDD
SR
t1 t2 t3 t4
SR 37.5 SR 37.5 SR - SR -
Input Clock at XTAL1
0.5 VDD
VIHX VILX
t1 tOSCDD
t2
t4
t3
Figure 21
Input Clock Timing
Data Sheet
73
V2.3, 2003-11
TC11IB
CPU Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter CPUCLK period CPUCLK high time CPUCLK low time CPUCLK rise time CPUCLK fall time Symbol Limits min max - - - 2.8 2.2 ns ns ns ns ns Unit
tCPUCLK 10.4
CC
t1 t2 t3 t4
CC CC CC CC
3 4.5 - -
0.5 VDD
0.9 VDD 0.1 VDD
CPUCLK
t1 tCPUCLK t2 t4 t3
Figure 22
CPUCLK Timing
Data Sheet
74
V2.3, 2003-11
TC11IB
Timing for eDRAM Refresh Cycle (Operating Conditions apply; CL = 50 pF) Parameter eDRAM retention time LMU eDRAM refresh cycle time ComDRAM eDRAM refresh cycle time Symbol Limits min max 16 1.6 0.8 ms s s - Unit
tTRET
CC
tREF CC - tREF CC -
Refresh Cycle Time tREF Refresh Refresh
eDRAM access
Access Cycle Time
Figure 23
eDRAM Refresh Cycle Timing
Data Sheet
75
V2.3, 2003-11
TC11IB
Timing for EBU_LMB Clock Outputs (Operating Conditions apply; CL = 50 pF) Parameter EBUCLK period1) EBUCLK high time EBUCLK low time EBUCLK rise time EBUCLK fall time ACLK period2) ACLK high time ACLK low time ACLK rise time ACLK fall time
1) 2)
Symbol
Limits min max - - - 2.5 2.5 - - - 3.5 2.5 10.4 4.5 3 - - 20 9 9 - -
Unit ns ns ns ns ns ns ns ns ns ns
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
CC CC CC CC CC CC CC CC CC CC
LMB Clock : EBUCLK Clock = 1:1 (EBU_EBUCON.BUSCLK = 00H). LMB Clock : ACLK Clock = 2:1 (EBU_BFCON.EXTCLK = 01H). If EBU_BFCON.EXTCLK = 10H, the duty cycle is 33%, not 50%.
EBUCLK / ACLK
0.5 VDD
0.9 VDD 0.1 VDD
t2 (t7) t1 (t6)
t3 (t8)
t5 (t10)
t4 (t9)
Figure 24
EBU_LMB Clock Output Timing
Data Sheet
76
V2.3, 2003-11
TC11IB
Timing for SDRAM Access Signals (Operating Conditions apply; CL = 30 pF) Parameter CKE high from EBUCLK CKE low from EBUCLK A(23:0) output valid from EBUCLK A(23:0) output hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK RAS low from EBUCLK RAS high from EBUCLK CAS low from EBUCLK CAS high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK Symbol Limits min max 7.0 7.0 8.0 - 7.0 7.0 7.0 8.0 7.0 8.0 7.5 7.5 7.0 7.0 7.7 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18
CC - CC - CC - CC 2.0 CC - CC - CC - CC - CC - CC - CC - CC - CC - CC - CC - CC 2.0 SR 0.6 SR 3.8
Data Sheet
77
V2.3, 2003-11
TC11IB
Write Access:
EBUCLK
t1
CKE A(23:0) CSx RAS CAS RD/WR BC(3:0) AD(31:0)
t3
t4
row
t5 t8 t7
column
t6
t10 t9 t12 t14
t11 t13
data (0)
t15 t16
data (n-1)
Read Access:
EBUCLK CKE
t3 t4
t2
A(23:0) CSx RAS
row
column
t6
t10
CAS RD/WR BC(3:0) AD(31:0)
t9
t13
t14
data (0)
t17 t18
data (n-1)
Figure 25
SDRAM Access Timing
Data Sheet
78
V2.3, 2003-11
TC11IB
Timing for Burst Flash Access Signals Operating Conditions apply; CL = 50 pF) Parameter A(23:0) output valid from ACLK A(23:0) output hold from ACLK CS(6:0) low from ACLK CS(6:0) high from ACLK ADV low from ACLK ADV high from ACLK BAA low from ACLK BAA high from ACLK RD low from ACLK RD high from ACLK AD(31:0) input setup to ACLK AD(31:0) input hold from ACLK Symbol Limits min max 11.0 - 9.0 9.0 10.0 10.0 10.0 10.0 12.0 10.0 - - ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
CC - CC 2.0 CC - CC - CC - CC - CC - CC - CC - CC - SR 8.0 SR 1.0
Note:WAIT signal is not characterized here because the TC11IB does not cover such cases.
Data Sheet
79
V2.3, 2003-11
Figure 26
Data Sheet
t2
ACLK
address
t4
t1
A(23:0)
CSx
t6
t3
Burst Flash Access Timing
t8 t7
ADV
t5
80
t9
BAA
RD
t10
AD(31:0)
data(0)
t11 t12
data(n-1)
V2.3, 2003-11
TC11IB
TC11IB
Timing for Demultiplexed Access Signals (Operating Conditions apply; CL = 50 pF) Parameter ALE low from EBUCLK ALE high from EBUCLK A(23:0) output valid from EBUCLK A(23:0) output hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK MR/W low from EBUCLK MR/W high from EBUCLK RMW low from EBUCLK RMW high from EBUCLK RD low from EBUCLK RD high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK CMDELAY input setup to EBUCLK CMDELAY hold from EBUCLK WAIT input setup to EBUCLK WAIT hold from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK Symbol Limits min max 8.0 8.0 8.0 - 8.0 8.0 8.0 8.0 16.5 16.5 8.0 8.0 8.0 8.0 - - - - 8.0 8.0 8.0 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24
CC - CC - CC - CC 2.0 CC - CC - CC - CC - CC - CC - CC - CC - CC - CC - SR 7.0 SR 5.5 SR 8.0 SR 5.5 CC - CC - CC - CC 2.0 SR 7.0 SR 3.5
Data Sheet
81
V2.3, 2003-11
Figure 27
Data Sheet
t2 t4
EBUCLK
t1
ALE
address
t3
A(23:0)
CSx
t5
t6
MR/W
t7
Write Access in Demultiplexed Access
82
t13 t15 t16 t17 t18 t19 t21
RD/WR
t14
CMDELAY
WAIT
t19
t20 t20
BC(3.0)
AD(31:0)
data
t22
V2.3, 2003-11
TC11IB
Figure 28
Data Sheet
t2 t4
EBUCLK
t1
ALE
address
t6
t3
A(23:0)
CSx
t5
MR/W
t8
RMW
t11
t9
t10 t12
Read Access in Demultiplexed Access
83
t15 t16 t17 t19 t18
RD
CMDELAY
WAIT
t19
t20
BC(3:0)
data
t23 t24
AD(31:0)
V2.3, 2003-11
TC11IB
Note: RMW signal is only available during Read-Modify-Write Access.
TC11IB
Timing for Multiplexed Access Signals (Operating Conditions apply; CL = 50 pF) Parameter ALE high from EBUCLK ALE low from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK MR/W low from EBUCLK MR/W high from EBUCLK RMW low from EBUCLK RMW high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK RD low from EBUCLK RD high from EBUCLK CMDELAY input setup to EBUCLK CMDELAY hold from EBUCLK WAIT input setup to EBUCLK WAIT hold from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK Symbol Limits min max 8.0 8.0 8.0 - - - 8.0 8.0 8.0 8.0 16.5 16.5 8.0 8.0 8.0 8.0 - - - - 8.0 8.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22
CC - CC - CC - CC 2.0 SR 7.0 SR 3.5 CC - CC - CC - CC - CC - CC - CC - CC - CC - CC - SR 7.0 SR 5.5 SR 6.0 SR 5.5 CC - CC -
Data Sheet
84
V2.3, 2003-11
Figure 29
t2 t4
Data Sheet
address
t4 t3
EBUCLK
t1
ALE
data
t8
t3
AD(31:0)
CSx
t7
MR/W
t9
Write Access in Multiplexed Access
t13 t18 t19 t21 t22 t20 t22 t14
85
RD/WR
CMDELAY
t17
WAIT
t21
BC(3.0)
V2.3, 2003-11
TC11IB
Figure 30
Data Sheet
t2 t5 t6
EBUCLK
t1
ALE
address
t4
t3
AD(31:0)
data
t8
CSx
t7
MR/W
t10 t12
Read Access in Multiplexed Access
86
t15 t17 t18 t19 t21 t20
RMW
t11
RD
t16
CMDELAY
WAIT
t21
t22
BC(3:0)
V2.3, 2003-11
TC11IB
Note: RMW signal is available only during Read-Modify-Write Access.
TC11IB
Timing for External Bus Arbitration Signals (Operating Conditions apply; CL = 50 pF) Parameter HOLD input setup to EBUCLK HOLD input hold from EBUCLK HLDA low from EBUCLK HLDA high from EBUCLK HLDA input setup to EBUCLK HLDA input hold from EBUCLK BREQ low from EBUCLK BREQ high from EBUCLK CS(6:0) drive from EBUCLK CS(6:0) high-impedance from EBUCLK Other signals high-impedance from EBUCLK Other signals drive from EBUCLK Symbol Limits min max - - 11.0 11.0 - - 9.5 9.5 8.0 8.0 8.0 8.0 ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
SR 6.0 SR 5.5 CC - CC - SR 6.4 SR 5.5 CC - CC - CC - CC - CC - CC -
Data Sheet
87
V2.3, 2003-11
Figure 31
Data Sheet
t2 t3 t8 t4 t9 t10 t12 t7 t9 t11 t8 t5 t6 t1 t2 t9 t10 t12 t11
External Master Mode:
EBUCLK
HOLD
t1
HLDA
BREQ
CSx
Other signals
External Bus Arbitration Timing
88
External Slave Mode:
EBUCLK
BREQ
t7
HLDA
HOLD
CSx
V2.3, 2003-11
Other signals
TC11IB
TC11IB
Port Timing (Operating Conditions apply; CL = 50 pF)
Parameter Port data valid from CPUCLK
1)
Symbol
1)
Limits min max 14.0 -
Unit ns
t1
CC
Port data is output with respect to the slow FPI clock at 48MHz. The CPUCLK is used as a reference here since the slow FPI clock is not available as an external pin. Port lines maintain its state for at least 2 CPU clocks.
CPUCLK
S_FPI_CLK
t1
Port Lines
Old State
New State
Figure 32
Port Timing
Data Sheet
89
V2.3, 2003-11
TC11IB
Timing for Ethernet Signals (Operating Conditions apply; CL = 50 pF) Parameter ETXCLK period (10 Mbps Ethernet) ETXCLK high time (10 Mbps Ethernet) ETXCLK low time (10 Mbps Ethernet) ETXCLK period (100 Mbps Ethernet) ETXCLK high time (100 Mbps Ethernet) ETXCLK low time (100 Mbps Ethernet) ERXCLK period (10 Mbps Ethernet) ERXCLK high time (10 Mbps Ethernet) ERXCLK low time (10 Mbps Ethernet) ERXCLK period (100 Mbps Ethernet) ERXCLK high time (100 Mbps Ethernet) ERXCLK low time (100 Mbps Ethernet) ERXD(3:0) input setup to ERXCLK ERXD(3:0) input hold from ERXCLK ERXDV input setup to ERXCLK ERXDV input hold from ERXCLK ERXER input setup to ERXCLK ERXER input hold from ERXCLK ETXD(3:0) output valid from ETXCLK ETXEN output valid from ETXCLK ETXER output valid from ETXCLK EMDC clock period EMDIO input setup to EMDC (sourced by STA) EMDIO input hold from EMDC (sourced by STA) EMDIO output valid from EMDC (sourced by PHY) Symbol Limits min max 260.0 260.0 26.0 26.0 260.0 260.0 26.0 26.0 10.0 10.0 10.0 25.0 25.0 25.0 10.0 300.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t1 t2 t3 t1 t2 t3 t1 t2 t3 t4 t5 t4 t5 t4 t5 t6 t6 t6 t7 t8 t9 t10
SR 400.0 SR 140.0 SR 140.0 SR 40.0 SR 14.0 SR 14.0 SR 400.0 SR 140.0 SR 140.0 SR 40.0 SR 14.0 SR 14.0 SR 10.0 SR SR 10.0 SR SR 10.0 SR CC CC CC CC 150.0 SR 10.0 SR CC -
Note: Any other parameters which are not stated here, please refer to ANSI/IEEE Std 802.3, Section 22.3.
Data Sheet
90
V2.3, 2003-11
TC11IB
t1
ETXCLK ERXCLK
t2 t3 t4 t5
ERXD(3:0) ERXDV ERXER
t6
valid data
ETXD(3:0) ETXEN ETXER
t7
valid data
EMDC
t8 t9
EMDIO (sourced by STA)
t10
valid data
EMDIO (sourced by PHY)
valid data
Figure 33
Ethernet Timing
Data Sheet
91
V2.3, 2003-11
TC11IB
Timing for MultiMediaCard Interface Signals (Operating Conditions apply; CL = 50 pF) Parameter MMCI.CLK period MMCI.CLK high time MMCI.CLK low time MMCI.CMD_RW output valid from MMCI.CLK MMCI.DAT_RW output valid from MMCI.CLK MMCI.ROD output valid from MMCI.CLK MMCI.VDDEN output valid from MMCI.CLK MMCI.CMD output valid from MMCI.CLK MMCI.DAT output valid from MMCI.CLK MMCI.CMD input setup to MMCI.CLK MMCI.DAT input setup to MMCI.CLK MMCI.CMD input hold from MMCI.CLK MMCI.DAT input hold from MMCI.CLK Symbol Limits min max - - - 4.0 3.0 4.0 2.0 33 33 - - 2.0 2.0 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t4 t4 t4 t4 t4 t5 t5 t6 t6
CC 62.5 CC 28 CC 28 CC - CC - CC - CC - CC - CC - SR 12 SR 10 SR - SR -
t1 MMCI.CLK t4 Output t5 Input
valid data
t2
t3
valid data
t6
Figure 34
MultiMediaCard Interface Timing
Data Sheet
92
V2.3, 2003-11
TC11IB
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Parameter SCLK clock frequency SCLK clock high time SCLK clock low time SCLK clock rise time SCLK clock fall time MTSR low/high from SCLK edge MRST setup to SCLK edge MRST hold from SCLK edge Symbol min. 1 / t SCLK t1 t2 t3 t4 t5 t6 t7 CC CC CC CC CC CC SR SR 18 18 13 7.5 Limit Values max. 24 11 11 2.0 MHz ns ns ns ns ns ns ns Unit
tSCLK t1 t2 t4 t3 0.9 VDD 0.1 VDD
SCLK
(CON.PO,CON.PH = 00 or 11)
SCLK
(CON.PO,CON.PH = 01 or 10)
t5
t2
t1
t3
t4 0.9 VDD 0.1 VDD
MTSR
State n-1
State n
State n+1
t6
t7 Data valid
MRST
Data valid
Figure 35
SSC Master Mode Timing
Data Sheet
93
V2.3, 2003-11
TC11IB
Timing for JTAG Signals (Operating Conditions apply; CL = 50 pF) Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time Symbol Limits min max - - - 0.4 0.4 ns ns ns ns ns 50 10 29 - - Unit
tTCK CC t1 CC t2 CC t3 CC t4 CC
0.5 VDD
0.9 VDD 0.1 VDD
TCK
t1 tTCK t2 t4 t3
Figure 36
TCK Clock Timing
Data Sheet
94
V2.3, 2003-11
TC11IB
Parameter TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK TDO high impedance to valid output from TCK TDO valid output to high impedance from TCK
Symbol
Limits min max - 1.0 - 1.0 29.0 23.0 26.0
Unit ns ns ns ns ns ns ns
t1 t2 t1 t2 t3 t4 t5
CC 7.85 CC - CC 10.9 CC - CC - CC - CC -
TCK
t2
t1
TMS
t2
t1
TDI
t4 t3 t5
TDO
Figure 37
JTAG Timing
Data Sheet
95
V2.3, 2003-11
TC11IB
Timing for OCDS Trace and Breakpoint Signals (Operating Conditions apply; CL = 50 pF) Parameter BRK_OUT valid from CPUCLK OCDS2_STATUS[4:0] valid from CPUCLK OCDS2_INDIR_PC[7:0] valid from CPUCLK OCDS2_BRKPT[2:0] valid from CPUCLK PCP_PC[15:0] valid from CPUCLK
1)
Symbol
Limits min max 17.0 7.0 7.0 7.0 7.0
Unit ns ns ns ns ns
1)
t1 t1 t1 t1 t2
CC - CC - CC - CC - CC -
PCP Trace signals are output with respect to the slow FPI clock at 48MHz. The CPUCLK is used as a reference here since the slow FPI clock is not available as an external pin. PCP Trace signals maintain its state for at least 2 CPU clocks.
CPUCLK
t1
t1 New State
CPU Trace Signals
Old State
t2
PCP Trace Signals
Old State
New State
Note:
CPU Trace Signals include BRK_OUT, OCDS2_STATUS[4:0], OCDS2_INDIR_PC[7:0] and OCDS_BRKPT[2:0]. PCP Trace Signals include PCP_PC[15:0].
Figure 38
OCDS Trace Signals Timing
Data Sheet
96
V2.3, 2003-11
TC11IB
PCI 33MHz, 3.3V Signaling (Operating Conditions apply; CL = 10 pF) Parameter Symbol Min. Max. Units Test condition mA mA Eqt'n 1
2)
Switching Current IOH(AC) -12VDDP High -17.1(VDDP VOUT)
0 < VOUT 0.3VDDP 1) 0.3VDDP < VOUT < 0.9VDDP 1) 0.7VDDP < VOUT < VDDP 1) 3) VOUT = 0.7VDDP 3) VDDP > VOUT 0.6VDDP 1) 0.6VDDP > VOUT > 0.1VDDP 1) 0.18VDDP > VOUT > 0
1) 3)
(Test Point) Switching Current IOL(AC) 16VDDP Low 26.7VOUT
mA 32VDDP mA mA Eqt'n 2
4)
(Test Point) Low Clamp Current High Clamp Current ICL ICH -25 + (VIN + 1)/(0.015) 25 + (VIN - VDDP -1)/ (0.015) 1 1
38VDDP mA mA mA
VOUT = 0.18VDDP 3) -3 < VIN -1 VDDP+4 > VIN VDDP+1
Output Rise Slew slewr Rate Output Fall Slew Rate
1)
4 4
V / ns 0.2VDDP - 0.6VDDP load 5) V / ns 0.6VDDP - 0.2VDDP load 5)
slewf
Refer to the V/I curves in Figure 39. Switching current characteristics for REQ and GNT are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST which are system outputs. "Switching Current High" specifications are not relevant to SERR, PME, INTA, INTB which are open drain outputs. Equation 1: IOH = (98/VDDP) . (VOUT - VDDP) . (VOUT + 0.4 VDDP), where 0.7 VDDP < VOUT < VDDP Maximum current requirements must be met as drivers pull beyond the first step voltage. Equations defining these maximums (1 and 2) are provided with the respective diagrams in Figure 40. The equation-defined maximums should be met by design. In order to facilitate testing, a maximum current test point is defined for each side of the output driver. Equation 2: IOL = (256/VDDP) . (VOUT) . (VDDP - VOUT), where 0 < VOUT < 0.18 VDDP
2) 3)
4)
Data Sheet
97
V2.3, 2003-11
TC11IB
5)
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition edge. The specified load (see Figure 41) is optional; i.e., the designer may choose to meet this parameter with an unloaded output as per revision 2.0 of the PCI Local Bus Specification. However, adherence to both max. and min. parameters is required. Rise slew rates does not apply to open drain outputs.
Pull Up VDDP 0.9VDDP Voltage (V) Test point VDDP
Pull Down
AC drive point Voltage (V)
DC Drive point
0.6VDDP 0.5VDDP DC Drive point
0.3VDDP AC drive point - 0.5 - 12VDDP Current (mA) - 48VDDP
0.1VDDP 1.5 16VDDP Current (mA)
Test point
64VDDP
IOH = (98/VDDP) * (VOUT - VDDP) * (VOUT + 0.4VDDP) where, VDDP > VOUT > 0.7VDDP
IOL = (256/VDDP) * VOUT * (VDDP - VOUT) where, 0 < VOUT < 0.18VDDP
Figure 39
V/I Curves for 3.3V Signaling
11ns (min) Overvoltage Waveform Voltage Source Impedence R = 29 3.3V Supply 4ns (max) 0V + 7.1V 7.1V p-to-p (minimum)
R
Input Buffer 62.5ns (16MHz)
V
+ 3.6V Evaluation Setup 7.1V p-to-p (minimum) Undervoltage Waveform Voltage Source Impedence R = 28 - 3.5V
Figure 40
Maximum AC Waveforms for 3.3V Signaling
Data Sheet
98
V2.3, 2003-11
TC11IB
pin
1/2 in. max.
output buffer VDDP 1K 10pF 1K
Figure 41
Load Circuit for Slew Rate Measurement
PCI Clock Specification (Operating Conditions apply; CL = 10 pF) Parameter CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate
1)
Symbol Min. tCYC tHIGH tLOW 30 11 11 1
Max. 4
Units Notes ns ns ns V/ns
2) 1)
In general, the PCI component must work with any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system so long as the clock edges remain "clean" (monotonic) and the minimum cycle, high and low times are not violated. The clock may only be stopped in a low state. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 42.
2)
tHIGH 0.6 VDDP 0.5 VDDP 0.4 VDDP 0.3 VDDP
tLOW
0.4VDDP p-to-p (min)
0.2 VDDP
Figure 42
Clock Specification
Data Sheet
99
V2.3, 2003-11
TC11IB
PCI 3.3V Timing Parameters (Operating Conditions apply; CL = 10 pF) Parameter CLK to signal valid delay - bused signals CLK to signal valid delay - point to point Float to active delay Active to Float delay Input setup time to CLK - bused signals Input setup time to CLK - point to point Input hold time from CLK
1) 2)
Symbol Min. tVAL 2
Max. 11 12
Units ns ns ns
Notes
1) 2) 3)
tVAL(PTP) 2 tON tOFF tSU tSU(PTP) tH 7 10, 12 0 2
1) 2) 3)
1) 4) 1) 4) 3) 5) 6)
28
ns ns ns ns
3) 5)
5)
Refer to Figure 43. Minimum times are evaluated with same load used for slew rate measurement (as shown in Figure 41). Maximum times are evaluated with the load circuits as illustrated in Figure 45. REQ and GNT are point to point signals and have different output valid delay and input setup times compared to bused signals. GNT has a setup of 10 and REQ has a setup of 12. All other signals are bused. For purposes of Active/Float timing measurements, the Hi-Z or "OFF" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Refer to Figure 44. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.
3)
4)
5) 6)
Data Sheet
100
V2.3, 2003-11
TC11IB
Measurement Conditions
VTH CLK VTEST tVAL Output Delay VSTEP output current leakage current Tri-state Output tON tOFF VTL
Figure 43
Output timing measurement conditions
VTH CLK VTEST VTL tSU INPUT VTEST tH VTH VMAX VTL
inputs valid VTEST
Figure 44
Input timing measurement conditions
Tval(max) Rising Edge pin 1/2 in. max.
Tval(max) Falling Edge 1/2 in. max.
output buffer 25 10pF 10pF 25
VDDP
Figure 45
Data Sheet
Load circuits for Maximum Clock to Signal Valid Delays
101 V2.3, 2003-11
TC11IB
Parameters for Measurement Conditions Symbol VTH VTL VTEST VSTEP (rising edge) VSTEP (falling edge) VMAX Input signal edge rate
1)
Value 0.6 VDDP 0.2 VDDP 0.4 VDDP 0.285 VDDP 0.615 VDDP 0.4 VDDP 1
Units V V V V V V V / ns
Notes
1) 1)
2)
The input test is done with 0.1 VDDP overdrive. Timing parameters must be met with no more
overdrive than this.
2)
VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters.
Data Sheet
102
V2.3, 2003-11
TC11IB
Package Outline Plastic Package, P-BGA-388-2 (SMD) (Plastic Ball Grid Array Package)
Figure 46
P-BGA-388-2 Package
Sorts of Packing Package outlines for tubes, trays, etc. are contained in Data Sheet "Package Information" SMD = Surface Mounted Device
Data Sheet
103
V2.3, 2003-11
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